Table of Contents

• Anton, a special-purpose machine for molecular dynamics simulationDavid E. Shaw, Martin M. Deneroff, Ron O. Dror, Jeffrey Kuskin, Richard H. Larson, John K. Salmon, Cliff Young, Brannon Batson, Kevin J. Bowers, Jack C. Chao, Michael P. Eastwood, Joseph Gagliardo, John P. Grossman, Richard C. Ho, Doug Ierardi, István Kolossváry, John L. Klepeis, Timothy Layman, Christine McLeavey, Mark A. Moraes, Rolf Mueller, Edward C. Priest, Yibing Shan, Jochen Spengler, Michael Theobald, Brian Towles, Stanley C. Wang. 1-12 [doi]
• Power provisioning for a warehouse-sized computerXiaobo Fan, Wolf-Dietrich Weber, Luiz André Barroso. 13-23 [doi]
• Making the fast case common and the uncommon case simple in unbounded transactional memoryColin Blundell, Joe Devietti, E. Christopher Lewis, Milo M. K. Martin. 24-34 [doi]
• Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architecturesWeirong Zhu, Vugranam C. Sreedhar, Ziang Hu, Guang R. Gao. 35-45 [doi]
• Virtual hierarchies to support server consolidationMichael R. Marty, Mark D. Hill. 46-56 [doi]
• Virtual private cachesKyle J. Nesbit, James Laudon, James E. Smith. 57-68 [doi]
• An effective hybrid transactional memory system with strong isolation guaranteesChi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Grasso Bronson, Jared Casper, Christos Kozyrakis, Kunle Olukotun. 69-80 [doi]
• Performance pathologies in hardware transactional memoryJayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood. 81-91 [doi]
• Meta:::TM::://TxLinux: transactional memory for an operating systemHany E. Ramadan, Christopher J. Rossbach, Donald E. Porter, Owen S. Hofmann, Bhandari Aditya, Emmett Witchel. 92-103 [doi]
• An integrated hardware-software approach to flexible transactional memoryArrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott. 104-115 [doi]
• Rotary router: an efficient architecture for CMP interconnection networksPablo Abad, Valentin Puente, José-Ángel Gregorio, Pablo Prieto. 116-125 [doi]
• Flattened butterfly: a cost-efficient topology for high-radix networksJohn Kim, William J. Dally, Dennis Abts. 126-137 [doi]
• A novel dimensionally-decomposed router for on-chip communication in 3D architecturesJongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das. 138-149 [doi]
• Express virtual channels: towards the ideal interconnection fabricAmit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha. 150-161 [doi]
• Carbon: architectural support for fine-grained parallelism on chip multiprocessorsSanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen. 162-173 [doi]
• Hardware atomicity for reliable software speculationNaveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig B. Zilles. 174-185 [doi]
• Core fusion: accommodating software diversity in chip multiprocessorsEngin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez. 186-197 [doi]
• Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubitsEric Chi, Stephen A. Lyon, Margaret Martonosi. 198-209 [doi]
• A 64-bit stream processor architecture for scientific applicationsXuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang. 210-219 [doi]
• Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessorsChristopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen. 220-231 [doi]
• ParallAX: an architecture for real-time physicsThomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman. 232-243 [doi]
• Architectural implications of brick and mortar silicon manufacturingMartha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin. 244-253 [doi]
• Aquacore: a programmable architecture for microfluidicsAhmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar, Steven Wereley, Stephen C. Jacobson. 254-265 [doi]
• Mechanisms for store-wait-free multiprocessorsThomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos. 266-277 [doi]
• BulkSC: bulk enforcement of sequential consistencyLuis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas. 278-289 [doi]
• Limiting the power consumption of main memoryBruno Diniz, Dorgival Olavo Guedes Neto, Wagner Meira Jr., Ricardo Bianchini. 290-301 [doi]
• Power model validation through thermal measurementsFrancisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau. 302-311 [doi]
• Thermal modeling and management of DRAM memory systemsJiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang. 312-322 [doi]
• ReCycle: : pipeline adaptation to tolerate process variationAbhishek Tiwari, Smruti R. Sarangi, Josep Torrellas. 323-334 [doi]
• Matrix scheduler reloadedPeter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black. 335-346 [doi]
• Late-binding: enabling unordered load-store queuesSimha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler. 347-357 [doi]
• Comparing memory systems for chip multiprocessorsJacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis. 358-368 [doi]
• Interconnect design considerations for large NUCA cachesNaveen Muralimanohar, Rajeev Balasubramonian. 369-380 [doi]
• Adaptive insertion policies for high performance cachingMoinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer. 381-391 [doi]
• Performance and security lessons learned from virtualizing the alpha processorPaul A. Karger. 392-401 [doi]
• Automated design of application specific superscalar processors: an analytical approachTejas Karkhanis, James E. Smith. 402-411 [doi]
• Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suiteAashish Phansalkar, Ajay Joshi, Lizy Kurian John. 412-423 [doi]
• VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualizationHyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn. 424-435 [doi]
• Ginger: control independence using tag rewritingAndrew D. Hilton, Amir Roth. 436-447 [doi]
• Transparent control independence (TCI)Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary. 448-459 [doi]
• Examining ACE analysis reliability estimates using fault-injectionNicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel. 460-469 [doi]
• Configurable isolation: building high availability systems with commodity multi-core processorsNidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith. 470-481 [doi]
• Raksha: a flexible information flow architecture for software securityMichael Dalton, Hari Kannan, Christos Kozyrakis. 482-493 [doi]
• New cache designs for thwarting software cache-based side channel attacksZhenghong Wang, Ruby B. Lee. 494-505 [doi]
• Mechanisms for bounding vulnerabilities of processor structuresNiranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam. 506-515 [doi]
• Dynamic prediction of architectural vulnerability from microarchitectural stateKristen R. Walcott, Greg Humphreys, Sudhanva Gurumurthi. 516-527 [doi]