Abstract is missing.
- Unifying on-chip and inter-node switching within the Anton 2 networkBrian Towles, J. P. Grossman, Brian Greskamp, David E. Shaw. 1-12 [doi]
- A reconfigurable fabric for accelerating large-scale datacenter servicesAndrew Putnam, Adrian M. Caulfield, Eric S. Chung, Derek Chiou, Kypros Constantinides, John Demme, Hadi Esmaeilzadeh, Jeremy Fowers, Gopi Prashanth Gopal, Jan Gray, Michael Haselman, Scott Hauck, Stephen Heil, Amir Hormati, Joo-Young Kim, Sitaram Lanka, James R. Larus, Eric Peterson, Simon Pope, Aaron Smith, Jason Thong, Phillip Yi Xiao, Doug Burger. 13-24 [doi]
- SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network orderingBhavya K. Daya, Chia-Hsin Owen Chen, Suvinay Subramanian, Woo-Cheol Kwon, Sunghyun Park, Tushar Krishna, Jim Holt, Anantha P. Chandrakasan, Li-Shiuan Peh. 25-36 [doi]
- Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recoveryGaurang Upasani, Xavier Vera, Antonio González. 37-48 [doi]
- MemGuard: A low cost and energy efficient design to support and enhance memory system reliabilityLong Chen, Zhao Zhang. 49-60 [doi]
- GangES: Gang error simulation for hardware resiliency evaluationSiva Kumar Sastry Hari, Radha Venkatagiri, Sarita V. Adve, Helia Naeimi. 61-72 [doi]
- Real-world design and evaluation of compiler-managed GPU redundant multithreadingJack Wadden, Alexander Lyashevsky, Sudhanva Gurumurthi, Vilas Sridharan, Kevin Skadron. 73-84 [doi]
- ArchRanker: A ranking approach to design space explorationTianshi Chen, Qi Guo, Ke Tang, Olivier Temam, Zhiwei Xu, Zhi-Hua Zhou, Yunji Chen. 85-96 [doi]
- Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architecturesYakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei, David Brooks. 97-108 [doi]
- SynFull: Synthetic traffic models capturing cache coherent behaviourMario Badr, Natalie D. Enright Jerger. 109-120 [doi]
- Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessorAshish Venkat, Dean M. Tullsen. 121-132 [doi]
- Navigating the cache hierarchy with a single lookupAndreas Sembrant, Erik Hagersten, David Black-Schaffer. 133-144 [doi]
- 2: A statistical compression cache schemeAngelos Arelakis, Per Stenström. 145-156 [doi]
- The Dirty-Block IndexVivek Seshadri, Abhishek Bhowmick, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry. 157-168 [doi]
- Going vertical in memory management: Handling multiplicity by multi-policyLei Liu, Yong Li, Zehan Cui, Yungang Bao, Mingyu Chen, Chengyong Wu. 169-180 [doi]
- Fine-grain task aggregation and coordination on GPUsMarc S. Orr, Bradford M. Beckmann, Steven K. Reinhardt, David A. Wood. 181-192 [doi]
- Enabling preemptive multiprogramming on GPUsIvan Tanasic, Isaac Gelado, Javier Cabezas, Alex Ramírez, Nacho Navarro, Mateo Valero. 193-204 [doi]
- Single-graph multiple flows: Energy efficient design alternative for GPGPUsDani Voitsechov, Yoav Etsion. 205-216 [doi]
- HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programsSimone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones, Gu-Yeon Wei, David Brooks. 217-228 [doi]
- Efficient digital neurons for large scale cortical architecturesJames E. Smith. 229-240 [doi]
- An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPsKarthik Swaminathan, Huichu Liu, Jack Sampson, Vijaykrishnan Narayanan. 241-252 [doi]
- STAG: Spintronic-Tape Architecture for GPGPU cache hierarchiesRangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan. 253-264 [doi]
- Memory persistencySteven Pelley, Peter M. Chen, Thomas F. Wenisch. 265-276 [doi]
- Reducing access latency of MLC PCMs through line stripingMorteza Hoseinzadeh, Mohammad Arjomand, Hamid Sarbazi-Azad. 277-288 [doi]
- HIOS: A host interface I/O scheduler for Solid State DisksMyoungsoo Jung, Wonil Choi, Shekhar Srikantaiah, Joonhyuk Yoo, Mahmut T. Kandemir. 289-300 [doi]
- Towards energy proportionality for large-scale latency-critical workloadsDavid Lo, Liqun Cheng, Rama Govindaraju, Luiz Andre Barroso, Christos Kozyrakis. 301-312 [doi]
- SleepScale: Runtime joint speed scaling and sleep states management for power efficient data centersYanpei Liu, Stark C. Draper, Nam Sung Kim. 313-324 [doi]
- Optimizing virtual machine consolidation performance on NUMA server architecture for cloud workloadsMing Liu, Tao Li. 325-336 [doi]
- Row-buffer decoupling: A case for low-latency DRAM microarchitectureSeongil O, Young Hoon Son, Nam Sung Kim, Jung Ho Ahn. 337-348 [doi]
- Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activationTao Zhang, Ke Chen, Cong Xu, Guangyu Sun, Tao Wang, Yuan Xie. 349-360 [doi]
- Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errorsYoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu. 361-372 [doi]
- Architecture implications of pads as a scarce resourceRunjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron. 373-384 [doi]
- Increasing off-chip bandwidth in multi-core processors with switchable pinsShaoming Chen, Yue Hu, Ying Zhang, Lu Peng, Jesse Ardonne, Samuel Irving, Ashok Srivastava. 385-396 [doi]
- A low power and reliable charge pump design for Phase Change MemoriesLei Jiang, Bo Zhao, Jun Yang, Youtao Zhang. 397-408 [doi]
- Fractal++: Closing the performance gap between fractal and conventional coherenceGwendolyn Voskuilen, T. N. Vijaykumar. 409-420 [doi]
- OmniOrder: Directory-based conflict serialization of transactionsXuehai Qian, Benjamin Sahelices, Josep Torrellas. 421-432 [doi]
- Pacifier: Record and replay for relaxed-consistency multiprocessors with distributed directory protocolXuehai Qian, Benjamin Sahelices, Depei Qian. 433-444 [doi]
- Replay debugging: Leveraging record and replay for program debuggingNima Honarmand, Josep Torrellas. 455-456 [doi]
- The CHERI capability model: Revisiting RISC in an age of riskJonathan Woodruff, Robert N. M. Watson, David Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G. Neumann, Robert Norton, Michael Roe. 457-468 [doi]
- CODOMs: Protecting software with Code-centric memory DomainsLluís Vilanova, Muli Ben-Yehuda, Nacho Navarro, Yoav Etsion, Mateo Valero. 469-480 [doi]
- EOLE: Paving the way for an effective implementation of value predictionArthur Perais, André Seznec. 481-492 [doi]
- Improving the energy efficiency of Big CoresKenneth Czechowski, Victor W. Lee, Ed Grochowski, Ronny Ronen, Ronak Singhal, Richard W. Vuduc, Pradeep Dubey. 493-504 [doi]
- General-purpose code acceleration with limited-precision analog computationRenée St. Amant, Amir Yazdanbakhsh, Jongse Park, Bradley Thwaites, Hadi Esmaeilzadeh, Arjang Hassibi, Luis Ceze, Doug Burger. 505-516 [doi]
- Race Logic: A hardware acceleration for dynamic programming algorithmsAdvait Madhavan, Timothy Sherwood, Dmitri B. Strukov. 517-528 [doi]
- Eliminating redundant fragment shader executions on a mobile GPU via hardware memoizationJose-Maria Arnau, Joan-Manuel Parcerisa, Polychronis Xekalakis. 529-540 [doi]
- WebCore: Architectural support for mobile Web browsingYuhao Zhu, Vijay Janapa Reddi. 541-552 [doi]