Abstract is missing.
- A Sigma-Delta Frequency Discriminator Based SynthesizerWalt T. Bax, Tom A. D. Riley, Calvin Plett, Miles A. Copeland. 1-4
- A Practical Second-Order Delta-Digma Frequency-to-Digital ConverterIan Galton. 5-8
- A Highly Linear Switched-Capacitor DAC for Multi-Bit Sigma-Delta D/A ApplicationsP. Ju, K. Suyama, P. Ferguson, W. Lee. 9-12
- Improved Delta-Sigma DAC Linearity Using Data Weighted AveragingRex T. Baird, Terri S. Fiez. 13-16
- A Novel Architecture for Reducing the Sensitivity of Multibit Sigma-Delta ADCs To DAC NonlinearityMervyn H. Adams, Chris Toumazou. 17-20
- A Novel High-Speed BiCMOS Domino Logic FamilyAnura P. Jayasumana, Yashwant K. Malaiya, Sankaran M. Menon. 21-24
- A New CMOS Current-Sensing Complementary Pass-Transistor Logic (CSCPTL) for High-Speed Low-Voltage ApplicationsChung-Yu Wu, Jr-Houng Lu, Kuo-Hsing Cheng. 25-28
- New Types of Digital ComparatorsJ. A. Hidalgo-López, J. C. Tejero, J. Fernández, A. Gago. 29-32
- Vertical Signal Transmission in Three-Dimensional Integrated Circuits by Capacitive CouplingStefan A. Kühn, Michael B. Kleiner, Roland Thewes, Werner Weber. 37-40
- Floorplanning with Datapath OptimizationAbdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman. 41-44
- Floorplanning for Low Power DesignsKai-Yuan Chao, D. F. Wong. 45-48
- A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical DesignsMorteza Saheb Zamani, Graham R. Hellestrand. 49-52
- Layout Optimization Using Arbitrarily High Degree Posynomial ModelsPiyush K. Sancheti, Sachin S. Sapatnekar. 53-56
- A Linear Arrangement Problem with ApplicationsWei-Liang Lin, Majid Sarrafzadeh. 57-60
- New IIR Digital Filter Realizations Using Residue-FeedbackA. Tawfik, Panajotis Agathoklis, Fayez El Guibaly. 61-64
- Analysis of Bilinear Digital Ladder FiltersSvante Signell, Lennart Harnefors. 69-72
- General, Linear Boundary Conditions in MD Wave Digital SimulationsKasyapa Balemarthy, Steven C. Bass. 73-76
- Synthesis and Pipelining of Ladder Wave Digital Filters in Digital DomainJin-Gyun Chung, Keshab K. Parhi. 77-80
- Optimal PN Sequences Design for Quasi-Synchronous CDMA Communication SystemsXuDuan Lin, KyungHi Chang, Jaeseok Kim. 81-84
- A High Speed 800 Channel Digital Interpolator NetworkC. A. Carty, M. M. Jamali, A. G. Eldin, Subhash C. Kwatra, R. E. Jones. 85-88
- Performance of a Quasi-Newton Adaptive Filtering Algorithm for a CDMA Indoor Wireless SystemS. Subramanian, Dale J. Shpak, Andreas Antoniou. 89-92
- Wideband Optical Fiber Signal Transmission System of 300MHz Bandwidth Using LEDNabil Abd Rabou, Hiroaki Ikeda, Hirofumi Yoshida. 93-96
- Bit-Error Rate Measurements for A High Frequency Interpolated Frequency-Hopping Spread-Spectrum SystemNorman M. Filiol, Calvin Plett, Tom A. D. Riley, Miles A. Copeland. 97-100
- A Method for Identifying Combinations of Transistors that can be Replaced with a Single Transistor when Applying the Nielsen-Willson TheoremMichael M. Green. 105-108
- Design-Oriented Analysis of CD Operating-Point InstabilityRobert M. Fox. 109-112
- Stability of a Circuit with Parasitic CapacitancesS. W. Ng, Y. S. Lee, C. K. Tse, S. C. Wong. 113-116
- Sufficient Conditions for Finding Multiple Operating Points for CD Circuits Using Continuation MethodsMichael M. Green, Robert C. Melville. 117-120
- Convergence Suppression and Divergence Facilitation: New Approach to Prune Hidden Layer and Weights of Feedforward Neural NetworksSyozo Yasui, Aleksander Malinowski, Jacek M. Zurada. 121-124
- Basic-Evolutive Algorithms for Neural Networks Architecture Configuration and TrainingJuan Seijas, José L. Sanz-González. 125-130
- Capabilities and Limitations of Feedforward Neural Networks with Multilevel NeuronsAleksander Malinowski, Tomasz J. Cholewo, Jacek M. Zurada. 131-134
- A Novel Approach to the Convergence of Unsupervised Learning AlgorithmsRuey-Wen Liu, Yih-Fang Huang, Xie-Ting Ling. 135-138
- Peak Detection in Hough Transform Via Self-Organizing LearningClifford Sze-Tsan Choy, Pui-Kin Ser, Wan-Chi Siu. 139-143
- Stability and Dynamics of Power Systems with Regulated ConvertersMohamed Belkhayat, Roger E. Cooley, Eyad H. Abed. 143-145
- Hard Limit Induced OscillationsX. Jiang, Heinz Schättler, John Zaborszky, Vaithianathan Venkatasubramanian. 146-150
- On the Computation of Hetero Clinic Orbits in Dynamical SystemsM. A. Pai, Mark Laufenberg. 151-154
- Approximation Algorithms for the k-Edge-Connectivity Augmentation ProblemToshiya Mashima, Toshimasa Watanabe. 155-158
- The Structure of Networks Realized from Terminal Capacity MatricesHiroshi Tamura, Ryohei Sato, Masakazu Sengoku, Shoji Shinoda, Takeo Abe. 159-162
- On Rectilinear Distance-Preserving TreesGustavo E. Téllez, Majid Sarrafzadeh. 163-166
- Floorplan Area Optimization Using Network Analogous ApproachKai Wang, Wai-Kai Chen. 167-170
- A Multi-Feedback Design for LC Bandpass Delta-Sigma ModulatorsOmid Shoaei, W. Martin Snelgrove. 171-174
- Delta-Sigma Converters Using Frequency-Modulated Intermediate ValuesMats Erling Høvin, Alf Olsen, Tor Sverre Lande, Chris Toumazou. 175-178
- Design of Thermal Sigma-Delta Modulators for Smart Thermal SensorsHuibert-Jan Verhoeven, Johan H. Huijsing. 179-182
- Low-Power High-Speed Continuous-Time Sigma-Delta ModulatorsRohit Mittal, David J. Allstot. 183-186
- A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing RecoveryMehmet Soyuer, Herschel A. Ainspan, John F. Ewen. 187-190
- A Digital PLL with Finite Impulse ResponsesFuminori Kobayashi, Masayuki Haratsu. 191-194
- A Wide-Range Progammable High-Speed CMOS Frequency DividerPatrik Larsson. 195-198
- A 550MHz 9.3mW CMOS Frequency DividerJiin-Chuan Wu, Hun-Hsien Chang. 199-202
- Performance Driven Routing with Mulitiple SourcesJason Cong, Patrick H. Madden. 203-206
- An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel RoutingShashidhar Thakur, Kai-Yuan Chao, D. F. Wong. 207-210
- An MCM Routing Algorithm Considering CrosstalkTetsuya Miyoshi, Shin ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida. 211-214
- Minimum-Cost Bounded-Skew Clock RoutingJason Cong, Cheng-Kok Koh. 215-218
- DSP Implememntation of Fast FIR Filtering Algorithms Using Short FFT sAnissa Zergaïnoh, Pierre Duhamel, Jean Pierre Vidal. 219-222
- An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two CoefficientsChao-Liang Chen, Kei-Yong Khoo, Alan N. Willson Jr.. 223-226
- Design of FIR Digital Filters with Minimum Weight RepresentationMitsuhiko Yagyu, Toshiyuki Yoshida, Akinori Nishihara, Nobuo Fujii. 227-230
- Low-Power FIR Digital Filter ArchitecturesDarren N. Pearson, Keshab K. Parhi. 231-234
- Visual Pattern BTC with Two Principle Colors for Color ImagesTak Po Chan, Bing Zeng, Ming L. Liou. 235-238
- Classification of Rotated and Scaled Textures by Local Linear OperationsW. K. Lam, C. K. Li. 243-246
- A Spectral Approach for Studying Spatio-Temporal ChaosMarco Gilli. 251-254
- A Hysteresis Hyperchaos Generator FamilyKunihiko Mitsubori, Toshimichi Saito. 259-262
- Chaos from Orbit-Flip Homoclinic Orbits Generated in Real SystemsHisa-Aki Tanaka, Kazuo Horiuchi, Shin ichi Oishi. 263-266
- Real-Time Application of Biology-Inspired Neural Networks Using and Emulator with Dedicated Communication HardwareM. Scholles, Bedrich J. Hosticka, Markus Schwarz. 267-270
- Implementation and Test Results of a Chip for the Separation of Mixed SignalsAmmar B. A. Gharbi, Fathi M. A. Salam. 271-274
- A Circuit for Learning in Fuzzy Logic-Based ControllersFrancisco Colodro Ruiz, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo. 279-286
- An Investigation of Invariant Properties of Unstable Equilibrium Points on the Stability Boundary for Simple Power System ModelsChia-Chi Chu, Hsiao-Dong Chiang, James S. Thorp. 287-290
- Damping and Incremental Energy in Thyristor Switching CircuitsRajesh Rajaraman, Ian Dobson. 291-294
- The Design of New Low-Voltage CMOS VHF Continuous-Time Lowpass Biquaud FiltersChung-Yu Wu, Heng-Shou Hsu. 295-298
- Log-Domain Filters Based on LC Ladder SynthesisD. Perry, Gordon W. Roberts. 311-314
- A CMOS CCII+Giuseppe Di Cataldo, Giovanni Palmisano, Gaetano Palumbo. 315-318
- Dynamic Amplifiers: Settling, Slewing and Power IssuesFeng Wang, Ramesh Harjani. 319-322
- A New BiCMOS Technique for Very Fast Discrete-Time Signal ProcessingPeter Shah, Chris Toumazou. 323-326
- 2-D IFIR Structures Using Generalized Factorable FiltersRoberto Manduchi. 327-330
- Frequency Shift of Two-Dimensional Real Coefficient Zero Phase Fir Digital FiltersPavel Zahradnik, Rolf Unbehauen. 331-334
- Design of 2-Dimensional Digital Filters Using 2-D All-Pass Building BlocksH. Safiri, Majid Ahmadi, V. Ramachandran. 340-343
- Design of 2-D IIR Filters Using a New Digital Spectral TransformationRajamohana Hegde, B. A. Shenoi. 344-347
- Error Spectrum Shaping in 2-D Digital FiltersTakao Hinamoto, Shuji Karino, Naoki Kuroda. 348-351
- New Algorithm for Structurally Balanced Model Reduction of 2-D Discrete SystemsHaiyun Luo, Songwu Lu, Andreas Antoniou. 352-355
- A Weighted Balanced Realization of 2-D Discrete SystemsHaiyun Luo, Songwu Lu, Andreas Antoniou. 357-360
- A New Filter Implementation Strategy for Lagrange InterpolationVesa Välimäki. 361-364
- A Realization Method of an ARMAX Lattice FilterMiki Haseyama, Tohru Hirohku, Hideo Kitajima. 365-368
- A Fuzzy Mean Field Approach for Partitioning and PlacementCarsten F. Ball, Andreas Just, Dieter A. Mlynski. 373-376
- Speed: Fast and Efficient Timing Driven PlacementBernhard M. Riess, Gisela G. Ettelt. 377-380
- Neural Network Based Estimation of VLSI Building Block Dimensions from SchematicXiao Quan Li, Marwan A. Jabri. 381-384
- Fault Orientated Test and Fault Simulation of Mixed Signal Integrated CircuitsIan M. Bell, Kevin R. Eckersall, Stephen J. Spinks, Gaynor E. Taylor. 389-392
- An I::DDQ:: Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs)Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee. 393-396
- On the VLSI Implementation of the International Data Encryption Algorithm IDEAStefan Wolter, Holger Matz, Andreas Schubert, Rainer Laur. 397-400
- High Speed, Fine Resolution Pattern Generation Using the Matched Delay TechniqueGary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III. 405-408
- A New Architecture for Analog Boundary ScanKuen-Jong Lee, Sheng-Yih Jeng, Tian-Pao Lee. 409-412
- An Analog VLSI Velocity SensorJörg Kramer, Rahul Sarpeshkar, Christof Koch. 413-416
- Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative MemoryChua-Chin Wang, Jeng-Ming Wu. 421-424
- On the Capacity of Intraconnected Bidirectional Associative MemoryBaoyun Wang, Luxi Yang, Hongtao Lu, Zhenya He. 425-428
- Dynamic Associative Memory Using Switched-Capacitor Chaotic NeuronsYoshihiko Horio, Ken Suyama. 429-432
- A Hardware Architecture for Video Rate Shading of Volume DataMichael C. Doggett, Graham R. Hellestrand. 433-436
- Generalized Multiplication Free Arithmetic CodesBin Fu, Keshab K. Parhi. 437-440
- A New Multilevel Codebook Searching Algorithm for Vector QuantizationHugh Q. Cao, Weiping Li. 441-444
- A Novel Closed Contour Extractor, Principle and AlgorithmA. Nabout, Bing Su, H. A. Nour Eldin. 445-448
- Fast Interframe Transfrom Coding Based on Characteristics of Transform Coefficients and Frame DifferenceYui-Lam Chan, Wan-Chi Siu. 449-452
- Lip Synchronization in 3-D Model Based Coding for Video-ConferencingJ. A. Provine, Leonard T. Bruton. 453-456
- A Region Based Motion Compensated Video Codec for Very Low Bitrate ApplicationsTouradj Ebrahimi, Homer H. Chen, Barry G. Haskell. 457-461
- Simple Cell Admission Control and Buffer Management Scheme for Mulitclass Video-On-Demand ServiceKeith Hung-Kei Chow, Ming L. Liou. 466-469
- A 3-D Integrator-Differentiator Double-Loop (IDD) Filter for Raster-Scan Video ProcessingR. K. Bertschmann, N. R. Bartley, Leonard T. Bruton. 470-473
- Total Least Squares Approach for Fast Learning in Multilayer Neural NetworksRaffaele Parisi, Elio D. Di Claudio, Gianni Orlandi. 474-477
- A Self-Organized Network with a Supervised TrainingYoshikazu Miyanaga, Honglan Jin, Rafiqul Islam, Koji Tochinai. 482-485
- Neural Network Approaches to fast and Low Rate Vector QuantizationJun Wang, Ce Zhu, Chenwu Wu, Zhenya He. 486-489
- Convergence of Hopfield Neural Network for Orthogonal TransformationTakeshi Kamio, Hiroshi Ninomiya, Hideki Asai. 493-496
- Lyapunov Function Based Fuzzy State EstimatorTzuu-Hseng S. Li, Chyi-Cherng Lai. 497-500
- Circulant Matrices and the Stability of Ring CNNsMark P. Joy, Vedat Tavsanoglu. 501-504
- Fast Learning by Weight Estimation in Complex Valued MLPsPaolo Arena, Luigi Fortuna, Giovanni Muscato, Maria Gabriella Xibilia. 505-508
- A Genetic Algorithm for Sex-Fair Stable Marriage ProblemMorikazu Nakamura, Kenji Onaga, Seiki Kyan, Manuel Silva. 509-512
- Equivalent Net Abstraction and Firing Sequence PreservationMasato Nakagawa, Dong-Ik Lee, Sadatoshi Kumagai, Shinzo Kodama. 513-516
- Petri-Net Methods for Reasoning in Real-Time Control SystemsTadao Murata, Jaegeol Yim. 517-520
- A Derivation of System Specifications Based on a Partial Logical Petri NetAtsushi Togashi, Nobuyuki Usui, Kukhwan Song, Norio Shiratori. 521-524
- Optimum Resolution-per-Stage in High-Speed Pipelined A/D Converters Using Self-CalibrationJoão Goes, João C. Vital, José E. Franca. 525-528
- New CMOS Logarithmic A/D Converters Employing Pipeline and Algorithmic ArchitecturesJorge Guilherme, José E. Franca. 529-532
- A Self-Calibrating A/D Converter Using T-Model Neural NetworkZheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno. 533-536
- A 1.5 V CMOS Current-Mode Cyclic Analog-to-Digital Converter with Digital Error CorrectionChih-Cheng Chen, Chung-Yu Wu, Jyh-Jer Cho. 537-540
- An Incremental A/C Converter for Accurate Vector Probe MeasurementsA. Häberli, Piero Malcovati, Henry Baltes, Franco Maloberti. 541-544
- A Digital-Serial VLSI Architecture for Delayed LMS Adaptive FIR FiltteringChin-Liang Wang, Ching-Chia Chen, Che-Fu Chen. 545-548
- A New Viterbi Decoder Design for Code Rate ::::K/N::::Hsiang-Ling Li, Chaitali Chakrabarti. 549-552
- A Waveront Array for URV Decomposition UpdatingArun Raghupathy, Ut-Va Koc, K. J. Ray Liu. 553-556
- Pipelined Adaptive IIR Filter ArchitectureNaresh R. Shanbhag, Gi-Hong Im. 558-561
- Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal ProcessorPeter Pirsch, Johannes Kneip, Karsten Rönner. 562-565
- Power-Up Delay for Retiming Digital CircuitsVigyan Singhal, Robert K. Brayton, Carl Pixley. 566-569
- Combining RC-Interconnect Effects with Nonlinear MOS MacromodelsJeong-Taek Kong, David Overhauser. 570-573
- A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory MultiprocessorsWen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su. 574-577
- Improving Digital MOS Macromodel AccuracyJeong-Taek Kong, Syed Zakir Hussain, David Overhauser. 578-581
- Automatic Dynamic Mixed-Mode Simulation Through Network ReconfigurationSyed Zakir Hussain, David Overhauser. 582-584
- Structures for Time Reversed Inversion in Filter BanksP. P. Vaidyanathan, Tsuhan Chen. 585-588
- IIR M-Th Band Filters with Allpass ComponentsT. Engin Tuncer, Truong Q. Nguyen. 593-596
- Mermite-like Reduction Method for Design of Perfect Reconstruction Multiband Linear Phase Filter BanksSankar Basu, Han-Mook Choi. 597-600
- Two-Layer MPEG Video Coding Algorithm for ATM NetworksJian Feng, Hassan Mehrpour, Kwok-Tung Lo, A. E. Karbowiak. 605-608
- Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMsMarco Winzker, Peter Pirsch, Jochen Reimers. 609-612
- A Block Matching Algorithm with 16: 1 Subsampling and Its Hardware DesignYanghoon Kim, Chong S. Rim, Byoungki Min. 613-616
- A High Accuracy Predictive Logarithmic Motion Estimation Algorithm for Video CodingMichael C. Chen, Alan N. Willson Jr.. 617-620
- A HDTV-Suited Architecture for a Fast Full Search Block-Matching AlgorithmStefan Honken, Feng-Ming Yang, Rainer Laur. 621-624
- Linearising Sigma-Delta Modulators Using Dither and ChaosChris Dunn, Mark B. Sandler. 625-628
- Proving Stability of Delta-Sigma Modulator Using Invariant SetsMontgomery Goodson, Bo Zhang, Richard Schreier. 633-636
- Bandpass Signal Generation Using Delta-Sigma Modulation TechniquesBenoît R. Veillette, Gordon W. Roberts. 637-640
- Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta SystemsPervez M. Aziz, Henrik V. Sorensen, Jan Van der Spiegel. 641-644
- Generalized Cellular Neural Networks Represented in he NL::::::q:::::: FrameworkJohan A. K. Suykens, Joos Vandewalle. 645-648
- VLSI Design of Cellular Neutral Networks with Annealing and Optical Input CapabilitiesBing J. Sheu, Sa Hyun Bang, Wai-Chi Fang. 653-656
- Realization of a CNN Universal Chip in CMOS TechnolgyServando Espejo-Meana, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez. 657-659
- Micromachined Display Ouptut for a Cellular Neural NetworkR. Yentis Jr., C. A. Zincke, Mona E. Zaghloul, M. Gaitan. 660-663
- From Circuit to Mechatronic System Tolerance OptimizationJacek Wojciechowski, Leszek J. Opalski, Krzysztof Zamlynski. 672-675
- Communication by Chaotic Signals: The Inverse System ApproachUte Feldmann, Martin Hasler, Wolfgang M. Schwarz. 680-683
- Synchronization of Chaotic Systems Through Parameter AdaptationPatrick Celka. 692-695
- Self-Calibration Technique for Pipe-Lined Algorithmic ADCK. Nagaraj. 696-699
- Error Correction Algorithm for Folding/Interpolation ADCHaruo Kobayashi, Hiroshi Sakayori, Tsutomu Tobari, Hiroyuki Matsuura. 700-703
- High-Speed, High-Reslution Analogue-To-Digital Conversion Using a Hybrid Electro-Optic ApproachRichard Mason, John T. Taylor. 704-707
- Measurement of Random Sample Time Jitter for ADCsDonald M. Hummels, Wahid Ahmed, F. H. Irons. 708-711
- An Efficient Memory Architecture for Motion Estimation Processor DesignEddie G. Tzeng, Chen-Yi Lee. 712-715
- A Novel Memory Architecture to Achieve Minimal Rounding/Truncation Errors for N Dimensional Image TransformationMin-Hsiung Lin, Gee-gwo Mei, Thomas A. Horvath, Robert J. Yagley, Roger S. Rutter. 716-719
- High-Level Estimation of High-Performance Architectures for Reed-Solomon DecodingYongjin Jeong, Wayne Burleson. 720-723
- Improving Parallel Circuit Simulation Using High-Level WaveformsYen-Cheng Wen, Kyle Gallivan, Resve A. Saleh. 728-731
- ADM: A New Technique for the Simulation of CMOS Circuit TransientsScott vpn Tonningen, Michael D. Ciletti. 732-735
- Simulation and Modelling of Nonlinear MagneticsMark C. Williams, Ronald S. Vogelsong, Kenneth S. Kundert. 736-739
- Orthogonalized Steepest Descent Method for Solving Nonlinear EquationsHiroshi Ninomiya, Hideki Asai. 740-743
- MDFT Filter Banks with Perfect ReconstructionT. Karp, Norbert J. Fliege. 744-747
- Modulated 2 Dimensional Perfect Reconstruction FIR Filter Banks with Permissible PassbandsHuan Yan, Masaaki Ikehara. 748-751
- Two-Dimensional Paraunitary Cosine Modulated Perfect Reconstruction Filter BanksYuan-Pei Lin, P. P. Vaidyanathan. 752-755
- Multidimensional Parallel Processing Methods for Rational Sampling Lattice AlterationShogo Muramatsu, Hitoshi Kiya. 756-759
- Power Complementary and Linear Phase Filter BanksKaoru Kurosawa, Naonori Yamashita. 760-763
- Automatic Determination of Scene Changes in MPEG Compressed VideoHain-Ching Liu, Gregory L. Zick. 764-767
- A Hybrid Coding Method for Digital HDTV SignalsPanos Nasiopoulos, Rabab Kreidieh Ward. 769-772
- An Adaptive Constrained Least Square Approach for Removing Blocking EffectSung-Wai Hong, Yuk-Hee Chan, Wan-Chi Siu. 773-776
- New Dyadic Transform for Image CompressionKwok-Tung Lo, Jian Feng. 777-780
- On Stability and the Lyapunov Equation for n-Dimensional Digital SystemsChengshan Xiao, David J. Hill, Panajotis Agathoklis. 781-784
- Asymptotic Stability of Linear Shift-Variant Difference Equations with Diamond-Shaped UncertaintiesS. A. Yost, Peter H. Bauer. 785-788
- Stability Test for 2-D LSI System Via a Unit Circle Test for Complex PolynomialsYuval Bistritz. 789-792
- Robust Pole Assignment for Discrete Interval SystemsOsman Ismail, B. Bandyopadhyay. 793-796
- Suppression of Spurious Responses for a Class of Neural Networks with Application to Telecommunications ProblemsRomano Fantacci, M. Forti, A. Liberatore, Stefano Manetti, Mauro Marini. 797-800
- Spaciotemporal Neural Networks for Shortest Path OptimizationJack L. Meador. 801-804
- A New Approach for Improving the Convergence Performance of Global Optimization ProblemsYong-Hyun Cho, Weon-Ook Kim, Hyun Koo Kang. 809-812
- A New Architecture for a Cyclic Algorithmic D/A ConverterDomine Leenaerts, Arjan J. Leeuwenburgh, G. G. Persoon, H. J. Reitsma. 821-824
- A CMOS Rail-to-Rail Linear VI-ConverterP. P. Vervoort, R. F. Wassenaar. 825-828
- A 3.3 Volt High-Frequency Capacitorless Electronically-Tunable Log-Domain OscillatorSitthichai Pookaiyaudom, Jirayuth Mahattanakul. 829-832
- Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC sMing-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Tao Cheng, Tain-Shun Wu. 833-836
- A Pixel Scale Digital to Analog Converter for Liquid Crystal on VLSI DisplaysAxel Thomsen, Robert Lindquist, Jeffrey H. Kulick, Patrick Nasiatka, Gregory Nordin, Stephen Kowel. 837-840
- Concurrent Self Test of Switched Current Circuits Based on the S:::2:::I-TechniqueGeir E. Sæther, Chris Toumazou, Gaynor E. Taylor, Kevin R. Eckersall, Ian M. Bell. 841-844
- An Analog High-Speed Wide-Range Programmable Monostable MultivibratorFranco Maloberti, S. Brigati, Giuseppe Caiulo, Guido Franchi, A. Bigongiari. 845-849
- An Analog VLSI Loser-Take-All CircuitGirish N. Patel, Stephen P. DeWeerth. 850-853
- A Loser-Take-All Error Amplifier for DC Power Supply ControlPaul D. Walker, Michael M. Green. 854-857
- Comparison of IIR Filter Structure Complexities Using Multiplier BlocksAndrew G. Dempster, Malcolm D. Macleod. 858-861
- IIR Notch Filtering - Comparisons of Four Adaptive Algorithms for Frequency EstimationT. S. Ng, Joe F. Chicharo. 865-868
- Design of Non-Uniformly Spaced Linear Phase FIR Filters Using Mixed Integer Linear ProgrammingJoon Tae Kim, Woo-Jin Oh, Yong-Hoon Lee. 877-880
- On Sigma-Delta Signal Processing Remodulator ComplexitySimon M. Kershaw, Steve Summerfield, Mark B. Sandler. 881-884
- Design of Optimal Linear-Phase Transmitter and Receiver Filters for Digital SystemsFrançois Moreau de Saint-Martin, Pierre Siohan. 885-888
- An Architecture for Integrated Reliability Simulators Using Analog Hardware Description LanguagesS. M. GadelRab, James A. Barby, Savvas G. Chamberlain. 897-900
- Estimating Node Voltages in Bipolar Circuits Using Linear ProgrammingElizabeth J. Brauer, Sung-Mo Kang. 901-903
- Modeling and Simulation of Hybrid Control Systems by Global Petri NetsMohammad Rezai, Mabo Robert Ito, P. D. Lawrence. 908-911
- GECO: A Tool for Automatic Generation of Error Control Codes for Computer ApplicationsLuca Penzo, Donatella Sciuto, Cristina Silvano. 912-915
- An Extension of the Tadeusiewicz Method for Finding Bounds on All Solutions of Piecewise-Linear EquationsTetsuo Nishi, Yuji Kawane. 916-919
- A Nonlinear Macromodel for CMOS OTAsGabriel J. Gómez, Sherif H. K. Embabi, Edgar Sánchez-Sinencio, Martin C. Lefebvre. 920-923
- Efficient Prototyping System Based on Incremental Design and Module-by-Module VerificationYongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jae-Hee Won, Kiyoung Choi. 924-927
- Tool Management in an Electronic CAD FrameworkJoão Camara, Helena Sarmento. 928-932
- Skew Safety and Logic Flexibility in a True Single Phase Clocked SystemPatrik Larsson. 941-944
- On Using Partial Reset for Pseudo-Random TestingMohamed Soufi, Yvon Savaria, Bozena Kaminska. 949-952
- A Decimation Filter Architecture for GHz Delta-Sigma ModulatorsColin Kuskie, Bo Zhang, Richard Schreier. 953-956
- State-Conditioned Rank-Ordered Filtering for Removing Impulse Noise in ImagesMichael Lightstone, Eduardo Abreu, Sanjit K. Mitra, Kaoru Arakawa. 957-960
- Adaptive L-Filters Based on Fuzzy RulesAkira Taguchi, Mitsuhiko Meguro. 961-964
- Design of Perfect Reconstruction QMF Banks by a Null-Space Projection MethodHua Xu, Wu-Sheng Lu, Andreas Antoniou. 965-968
- Design of Low-Delay Perfect-Reconstruction FIR Filter Banks for Tree-Structured Subband CodersEsam Abdel-Raheem, Fayez El Guibaly, Andreas Antoniou. 969-972
- Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural NetworksYuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.. 977-980
- Defuzzifier Circuits Using Resonant Tunneling DiodesHao Tang, Hung Chang Lin. 981-984
- Analog Encoding Circuits for a Digital CMOS Neural OscillatorBrannon C. Harris, Stephen P. DeWeerth. 989-992
- Response Characteristic from an Artificial Hysteresis NeuronNobuyuki Sanada, Toshimichi Saito. 993-996
- A New Type of Chaotic Attractor with Cellular Neural NetworksHongtao Lu, Luxi Yang, Baoyun Wang, Zhenya He. 997-1000
- Bifurcation Phenomena from a Simple Hysteresis NetworkKenya Jin no. 1001-1004
- Signal Transmission through a Chain of Chua s CircuitsMakoto Itoh, Hiroyuki Murakami, Leon O. Chua. 1005-1008
- Chaos Synchronization of High-Dimensional Dynamical SystemsLjupco Kocarev. 1009-1012
- Synchronization and Control of Chaos by Occasional Linear ConnectionToshimichi Saito, Hiroyuki Torikai, Kenya Jin no. 1013-1016
- Low Voltage SC Circuit Design with Low-V::t:: MOSFETsSeyfi S. Bazarjani, W. Martin Snelgrove. 1021-1024
- A 1.5V CMOS Balanced Differential Switched-Capacitor Filter with Internal Clock BoostersChung-Yu Wu, Wei-Shinn Wey, Tsai-Chung Yu. 1025-1028
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- A Lattice/Transversal Joint (LTJ) Structure for an Acoustic Echo CancellerJae Ha Yoo, Sung Ho Cho, Dae Hee Youn. 1090-1093
- A Real-Time Lossless Data Compression Technology for Remote-Sensing and Other ApplicationsPen-Shu Yeh, Warner H. Miller. 1098-1101
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- Lossless Compression of Seismic Signals Using Least Square Frequency Domain Pole-Zero ModelingYousef W. Nijim, Wasfy B. Mikhael, Samuel D. Stearns. 1106-1109
- Image Coding with the Wavelet TransformMark A. Coffey, Delores M. Etter. 1110-1113
- PWM and PCM Techniques for Control of Digitally Programmable Switching Power SuppliesGregory M. Cooley, Terri S. Fiez, Bryan Buchanan. 1114-1117
- Resonant dc/dc Converter with Class E Inverter and Class E Synchronous Rectifier Using Thinned-Out MethodMotoki Fujii, Tadashi Suetugu, Hirotaka Koizumi, Kokichi Shinoda, Shinsaku Mori. 1119-1122
- Large-Signal Stability of PWM Switching RegulatorsHenry Chung, Adrian Ioinovici. 1123-1126
- Estimation of Switch Statuses for Radical Power Distribution SystemsA. Abur, D. Shirmohammadi, C. S. Cheng. 1127-1130
- Dynamics of Minimal Power System Model - Invariant Tori and Quasi-Periodic MotionsWeijun Ji, Vaithianathan Venkatasubramanian. 1131-1135
- Qualitative Analysis of Hopfield Neural Nets with Delays: Global and Local ResultsHui Ye, Anthony N. Michel, Kaining Wang. 1136-1139
- Existence and Stability of a Unique Equilibrium in Continuous-Valued Discrete-Time Asynchronous Hopfield Neural NetworksAmit Bhaya, Eugenius Kaszkurewicz, V. S. Kozyakin. 1140-1143
- On Dynamics of a Learning Associative MemoryHuanglin Zeng, Roman W. Swiniarski. 1144-1147
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- Associative Dynamics of Competitive Cellular Neural NetworkMitsuhisa Kanaya, Masako Takahira, Toshirou Watanabe, Cong-Kha Pham, Mamoru Tanaka. 1152-1155
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- A Universal Interface Between PC and Neural Networks HardwareApollo Q. Fong, Ajay Kanji, Edgar Sánchez-Sinencio, José Pineda de Gyvez. 1169-1172
- VLSI Implementation of a Wavelet Image Compression Technique Using Replicated Coding/Decoding CellsJavier Veda-Pineda, Sergio D. Cabrera, Yi-Chieh Chang. 1173-1176
- Identification and Control of Chaotic Systems: An Artificial Neural Network ApproachGuanrong Chen, Xiaoning Dong. 1177-1182
- Signal Coding and Compression Based on Chaos Control TechniquesHervé Dedieu, Maciej Ogorzalek. 1191-1194
- Analog Filter Banks with Low Intermodulation DistortionJames A. Cherry, W. Martin Snelgrove. 1195-1198
- A New BiCMOS Low-Voltage and Low-Distortion OTA for Continuous-Time FiltersF. Yang, Christian C. Enz, D. Python. 1199-1202
- The Active-R Filter Technique Applied to Current-Feedback Op-AmpsChris Toumazou, Alison Payne, Sitthichai Pookaiyaudom. 1203-1206
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- Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition GraphsSung Tae Jung, Eun Sei Park, Jung Sik Kim, Chu Shik Jhon. 1211-1214
- Synthesis of Reliable Application Specific Heterogeneous MultiprocessorsAurobindo Dasgupta, Ramesh Karri. 1215-1218
- Performance Driven Technology Mapper for FPGAs with Complex Logic Block StructuresJun-Yong Lee, Eugene Shragowitz. 1219-1222
- Logic Reduction in Timed Asynchronous CircuitsUwe F. Baake, Sorin A. Huss. 1223-1226
- A Bayesian Approach to Variable Screening for Modeling the IC Fabrication ProcessXinhui Niu, Jay B. Brockman. 1227-1230
- Applications of the Piecewise Ellipsoidal Approximation to the Design of Nonlinear CircuitsJacek Wojciechowski, Leszek J. Opalski, Krzysztof Zamlynski. 1231-1234
- Symbolic Analysis for Fault Detection in Switch-Level CircuitsLluis Ribas, Jordi Carrabina. 1235-1238
- The All-Minors VCCS Matrix Tree Theorem, Half-Resistors and Applications in Symbolic SimulationSeth Chaiken, Paliath Narendran. 1239-1242
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- Leaky LMS: A Detailed AnalysisK. A. Mayyas, Tyseer Aboulnasr. 1255-1258
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- A General Purpose Discrete-Time Multiplexing Neuron-Array ArchitectureGunhee Han, Edgar Sánchez-Sinencio. 1320-1323
- A 1.6V 10-Bit 20MHz Current-Mode Sample and Hold CircuitYasuhiro Sugimoto. 1332-1335
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- A Robust Parallel Delta-Sigma A/D Converter ArchitectureHenrik T. Jensen, Ian Galton. 1340-1343
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- Parallel Digital Signal Filtering on Barrel Shifter ComputersG. Angelopoulos, Ioannis Pitas. 1368-1371
- Automated Programming of a Ring-Structured Multiprocessor Digital Filter ICMichael J. Werter, Alan N. Willson Jr.. 1372-1375
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- A Variable Step Size Algorithm with Generate-and Evaluate FunctionC. Y. Chung, Sin Chun Ng, Shu Hung Leung, Andrew Luk. 1380-1383
- Trellis-Based Deconvolution of Ultrasonic EchoesRichard Gut, Peter Kreier, George S. Moschytz. 1384-1387
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- Chip-Level Thermal Simulator to Predict VLSI Chip TemperatureYi-Kan Cheng, Sung-Mo Kang. 1392-1395
- Model Reduction of Linear Interval Systems Using Padé ApproximationOsman Ismail, B. Bandyopadhyay. 1400-1403
- Decomposition-Based Model Parameter ExtractionKatarzyna Opalska, Leszek J. Opalski. 1404-1407
- Accurate Semi-Symbolic Analysis of Large Non-Ideal Switched Linear NetworksJohn I. Sewell, Z. Q. Shang. 1408-1411
- Differential-Difference Equations for the Transient Simulation of Lossy MTLsIvan A. Maio, Flavio G. Canavero. 1412-1415
- A New Parallel Algorithm for Solving Sparse Linear SystemsK. N. Balasubramanya Murthy, C. Siva Ram Murthy. 1416-1419
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- A Cepstrum Chip: Architecture and ImplementationAn-Nan Suen, Jhing-Fa Wang, Yuen-Lin Chiang. 1428-1431
- VLSI Implementation of Very-High-Order FIR FiltersMichael A. Soderstrand, Kamal Al-Marayati. 1436-1439
- Two VLSI Design Advances in Arithmetic CodingBin Fu, Keshab K. Parhi. 1440-1443
- A New Block Adaptive Filtering Algorithm for Decision-Feedback Equalization of Multipath Fading ChannelsTerence Wang, Chin-Liang Wang. 1444-1447
- Digital Loop Extension Using Mid Span AmplificationGreg J. Erker, David E. Dodds, Witold A. Krzymien. 1452-1455
- Performance Analysis and Optimal Structuring of Subchannels for Discrete Multitone TransceiversAdil Benyassine, Ali N. Akansu. 1456-1459
- Matched-Filter Processing of Microphone Array for Spatial Volume SelectivityEa-Ee Jan, Piergiorgio Svaizer, J. L. Flanagan. 1460-1463
- A Sliding and Variable Window Based Multitone Excision for Digital Audio BroadcastingMichael Meyer, Mehmet V. Tazebay, Ali N. Akansu. 1464-1467
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- Spatiotemporal Chaos in Four Chaotic Circuits Coupled by One ResistorYoshifumi Nishio, Akio Ushida. 1472-1475
- Direct Analysis of Multiphase Switched-Current Networks Using Signal-Flow GraphsMarkus Helfenstein, Arnold Muralt, George S. Moschytz. 1476-1479
- Zero State Response of Linear Circuits to Exponential InputsAjoy Opal, Kaamran Raahemifar. 1484-1487
- Robust Stability of Linear Time-Delay Systems: Retarded and Neutral TypesHui Ye, Anthony N. Michel, Kaining Wang. 1488-1491
- All Pass Function Based Stability Test for Delta-Operator Formulated Discrete-Time SystemsHari C. Reddy, George S. Moschytz, Allen R. Stubberud. 1492-1495
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- On the Use of Loop Equations in Power System AnalysisAntonio Gómez Expósito, Ali Abur, Esther Romero Ramos. 1504-1507
- Study of Multisolution Quadratic Load Flow Problems and Applied Newton-Raphson Like MethodsYuri V. Makarov, Ian A. Hiskens, David J. Hill. 1508-1511
- Design of a Compact Cluster Structure by Using Genetic AlgorithmsHonglan Jin, Yoshikazu Miyanaga, Koji Tochinai. 1512-1515
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- Chaos as a Design Tactic: Broadening the Capture Range to the Phase-Locked LoopElizabeth Bradley, Douglas E. Straub. 1532-1535
- +/- 1V CMOS Rail to Rail Op AmpSuma Setty, Chris Toumazou. 1540-1543
- A Low-Voltage CMOS Op Amp with Rail-to-Rail Constant-gm Input Stage and High-Gain Output StageAbdulkerim L. Coban, Phillip E. Allen. 1548-1551
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- Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic CircuitsHong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu. 1572-1575
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- A Hyperstable Adaptive Line Enhancer for Frequency EstimationMukund Padmanabhan. 1600-1603
- A Unified Approach to Split Structure Adaptive FilteringP. C. Ching, K. F. Wan. 1604-1607
- A New Frequency-Domain LMS Adaptive Filter with Reduced-Sized FFT sHiroshi Ochi, Neil J. Bershad. 1608-1611
- On the Comparison of Optimum Least-Squares and Computationally Efficient DFT-Based Adaptive Block FiltersPius Estermann, August Kaelin. 1612-1615
- Finite Precision Analysis of the Fast QRD-RLS Lattice AlgorithmMarcio G. Siqueira, Abeer A. Alwan, Paulo S. R. Diniz. 1616-1619
- Super High Definition Image Coding Using Successive Approximation Wavelet Vector QuantizationEduardo A. B. da Silva, Demetrios G. Sampson, Mohammed Ghanbari. 1620-1623
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- VLSI Neural Network Implementation of a Hippocampal ModelBing J. Sheu, Theodore W. Berger, Tony H. Wu, Richard H. Tsai. 1664-1667
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- A Graph Theoretic Approach to Feed-Through Pin AssignmentYao-Ping Chen, D. F. Wong. 1687-1690
- Incremental Node Extraction Algorithms for Incremental Layout SystemMyong H. Cynn, Sung-Mo Kang. 1691-1694
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- Application of Generalized Radial Basis Functions In Speaker Normalization and IdentificationCesare Furlanello, Diego Giuliani, Edmondo Trentin, Daniele Falavigna. 1704-1707
- A New Learning Algorithm for RBF Neural Networks with Applications to Nonlinear System IdentificationShaohua Tan, Jianbin Hao, Joos Vandewalle. 1708-1711
- Prediction of Wood Pulp kappa# with Radial Basis Function Neural NetworkMohamad T. Musavi, D. R. Coughlin, M. Qiao. 1716-1719
- The Design of High Performance Low Cost BiCMOS Op-amps in a Predominantly CMOS TechnologyFrode Larsen, Mohammed Ismail. 1720-1723
- Limiting Circuits for Rail-To-Rail Output Stages of Low-Voltage Bipolar Operational AmplifiersKlaas-Jan de Langen, Jeroen Fonderie, Johan H. Huijsing. 1728-1731
- 90Db, 90MHz, 30m W OTA with the Gain-Enhancement Implemented by One and Two Stage AmplifiersMarkus Helfenstein, Qiuting Huang, George S. Moschytz. 1732-1735
- Retiming of Circuits Containing MultiplexersSven Simon, Johann Hofner, Josef A. Nossek. 1736-1739
- Retiming for BIST-Sequential CircuitsSamir Lejmi, Bozena Kaminska, Bechir Ayari. 1740-1743
- PLATO P: PLA Timing Optimization by PartitioningShihming Liu, Massoud Pedram, Alvin M. Despain. 1744-1747
- Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register DelayTolga Soyata, Eby G. Friedman, James H. Mulligan Jr.. 1748-1751
- SWANN - A Program for Analysis of Switched Analog Nonlinear NetworksJuraj Valsa, Jiri Vlach. 1752-1755
- Fast and Accurate Event Driven Simulation of Partly Analog Phase-Locked LoopsPatrik Larsson. 1756-1759
- Simulating Phase Noise in Phase-Locked Loops with a Circuit SimulatorWalter E. Thain, J. Alvin Connelly. 1760-1763
- Fault Simulation of an OTA Biquadratic FilterAndrew Bishop, André Ivanov. 1764-1767
- Subband Acoustic Echo Cancellation Using a Thin Lattice StructureM. Tahernezhadi, S. C. Manapragada, J. Liu. 1768-1771
- Steady-Stae Analysis of a Second-Order Adaptive IIR Notch Filter Using the Sign AlgorithmShotaro Nishimura, Koji Matsutani. 1776-1779
- A Family of Consistent Steiglitz-McBride Algorithms for IIR Adaptive FilteringPaulo S. R. Diniz, Juan E. Cousseau. 1780-1783
- A Subband Coding Method for HDTVWilson C. Chung, Faouzi Kossentini, Mark J. T. Smith. 1784-1787
- Subband Coding of Color Images Using Multiplierless Encoders and DecodersFaouzi Kossentini, Wilson C. Chung, Mark J. T. Smith. 1792-1795
- Multiwavelet Filter Banks for Data CompressionPeter N. Heller, Vasily Strela, Gilbert Strang, Pankaj Topiwala, Christopher Heil, L. S. Hills. 1796-1799
- Elimination of Mutual Couplings in Discrete Element Networks Arising from the Modeling of High Speed Digital InterconnectionsGuy Coen, Daniel De Zutter. 1800-1803
- Nonlinear Dynamics in a Distributed CircuitG. Guida, G. Miano, L. Verolino. 1804-1807
- Sampling of Quadrature-Phase QuantitiesLennart Harnefors, Kåre Mossberg. 1808-1811
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- The Investigation of Using Limited Precision on a TDNN for Consonant RecognitionWilliam Robertson, Selçuk Sen, William J. Phillips. 1820-1823
- Fault Detection and Classification of Analog Circuits by Means of Fuzzy Logic-Based TechniquesAntonio Jesús Torralba Silgado, Jorge Chávez Orzáez, Leopoldo García Franquelo. 1828-1831
- Time-Domain Model of Transmission Lines with Arbitrary Initial Potential and Current Distributions for Transient AnalysisJun-Fa Mao, Omar Wing, Fung-Yuel Chang. 1832-1835
- A Mathematical and Lumped-Element Model for Multiple Cascaded Lossy Transmission Lines with Arbitrary Impedances and DiscontinuitiesScott D. Huss. 1844-1847
- CMOS Circuits for On-Chip Capacitance Ratio Testing or Sensor ReadoutYuming Cao, Gabor C. Temes. 1848-1851
- A High Performance Low Voltage Switched-Current MultiplierG. H. M. Joordens, J. A. Hegt, Domine Leenaerts. 1856-1859
- One-Dimensional Model of the Power Bipolar Transistor with Thermoelectrical Interactions for Circuit ApplicationsT. Maurel, R. Bouchakour, Christophe Lallement. 1860-1863
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- On the Design of Active GaAs MultipliersT. L. Lim, David G. Haigh, D. R. Webster. 1872-1875
- Time Frequency Split Zak Transform for Finite Gabor ExpansionSoo-Chang Pei, Min-Hung Yeh. 1876-1879
- Transient Analysis Via Fast Wavelet-Based ConvolutionWai-Hung Leung, Fung-Yuel Chang. 1884-1887
- Subband Model and Implementation of 0-QAM SystemX. Q. Gao, H. Zhang, Z. Y. He. 1888-1891
- On the Convolution Property of a New Discrete Radon Transform and its Efficient Inversion AlgorithmDaniel Pak-Kong Lun, Tai-Chiu Hsung, Wan-Chi Siu. 1892-1895
- Jordan Decomposition FiltersDinu Coltuc, Ioannis Pitas. 1896-1899
- Fibonacci P-Code Method for Generalized Stack FilteringJaakko Astola, Pauli Kuosmanen, David Akopian, David Z. Gevorkian. 1900-1903
- On Time-Domain Deconvolution and the Computation of the CepstrumEduard Krajnik. 1908-1911
- Scan Chain Fault Diagnosis with Fault DictionariesGeetani Edirisooriya, Samantha Edirisooriya. 1912-1915
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- A Processor Core for 32 kbit/s G.726 ADPCM CodecsJuhani Vehvilainen, Jari Nurmi. 1932-1935
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- Application of Fast Orthogonal Search for the Design of RBFNNWahid Ahmed, Donald M. Hummels, Mohamad T. Musavi. 1952-1955
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- Approximation of Inverse Maps through RBF Neural NetworksAndrea Caiti, T. Parsini. 1960-1963
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- A New Mixer Circuit Using a Gate-Controlled LPNP BJTM. Jamal Deen, Duljit S. Malhi, Zhixin Yan, Robert A. Hadaway. 1968-1971
- A Low-Voltage, Bulk-Driven MOSFET Current Mirror for CMOS TechnologyBenjamin J. Blalock, Phillip E. Allen. 1972-1975
- A Design Scheme to Stabilize the Active Gain Enhancement AmplifierFan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio, A. Ganesan. 1976-1979
- Novel Circuit Solutions for Rail-to-Rail CMOS BufferGiuseppe Caiulo, Piero Malcovati, C. Bona, Franco Maloberti. 1980-1983
- A New Method of Implementation of VLSI CORDIC for Sine and Cosine ComputationHao-Yung Lo, Hsiu-Feng Lin, Kuen-Shiuh Yang. 1984-1987
- Merged CORDIC AlgorithmShaoyun Wang, Earl E. Swartzlander Jr.. 1988-1991
- A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal ApproximationI. Orginos, Vassilis Paliouras, Thanos Stouraitis. 1992-1995
- High-Speed Division Algorithm for Residue Number SystemAhmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy. 1996-1999
- Bit-Serial Dual Basis Systolic Multipliers for GF 2:::m:::Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor. 2000-2003
- Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault PartitioningJer Min Jou, Shung-Chih Chen. 2004-2007
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- Data Path Testability Analysis Based on BDDsGiacomo Buonanno, Fabrizio Ferrandi, Donatella Sciuto. 2012-2014
- A BDD Based Algorithm for Detecting Difficult FaultsCristiana Bolchini, Franco Fummi, R. Gemelli, Fabio Salice. 2015-2018
- A New Approach for the Selection of Test Points for Fault DiagnosisMohamed A. El-Gamal, Abdel-Karim S. O. Hassan, Hany L. Abdel-Malek. 2019-2022
- Design of Finite-Wordlength IIR Digital Filters in the Time/Spatial DomainJong-Jy Shyu, Yuan-Chih Lin. 2027-2030
- Simultaneous Minimization of Pole and Zero Sensitivity in Digital Filter DesignGang Li, Guoan Bi. 2031-2034
- An Exhaustive Search Algorithm for Checking Limit Cycle Behavior of Digital FiltersKamal Premaratne, E. C. Kulasekere, Peter H. Bauer, L. J. Leclerc. 2035-2038
- Weighted Sensitivity Minimization Synthesis of 2-D Filter Structures Using the Fornasini-Marchesini Second ModelTakao Hinamoto, Hirofumi Yamada, Yoshitaka Zempo. 2039-2042
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- Optimizing the Design of Switch-Mode Power Supplies with Battery Back-Up and Power Factor CorrectionY. S. Lee, K. W. Siu, Xuan-Zhong Liu. 2051-2054
- Compensating Networks for Sliding-Mode ControlRoberto Giral, Luis Martínez, Javier Hernanz, Javier Calvente, Francesc Guinjoan, Alberto Poveda, R. Leyva. 2055-2058
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- A New Symbolic Program of Package for the Interactive Design of Analog CircuitsA. Liberatore, Antonio Luchetta, Stefano Manetti, Maria Cristina Piccirilli. 2209-2212
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