Table of Contents

• Computational Neurobiology Meets Semiconductor EngineeringDan W. Hammerstrom. 3 [doi]
• Multi-Valued Logic Pass Gate Network Using Neuron-MOS TransistorsJing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka. 15-20 [doi]
• The Synthesis of Multiple-Valued Logic Circuits Using Local-Excitation-Type Neuron ModelsMasayuki Matsumoto, Yoshinori Ueda, Isami Nomoto. 21-26 [doi]
• Multi-Input Variable-Threshold Circuits for Multi-Valued Logic FunctionsMakoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka. 27-32 [doi]
• The Computing Capacity of Three-Input Multiple-Valued One-Threshold PerceptronsAlioune Ngom, Ivan Stojmenovic, Ratko Tosic. 33 [doi]
• MDD-Based Synthesis of Multi-Valued Logic NetworksRolf Drechsler, Mitchell A. Thornton, David Wessels. 41-46 [doi]
• Fast Transforms for Multiple-Valued Input Binary Output PLI LogicBogdan J. Falkowski, Susanto Rahardja. 47-52 [doi]
• Computation of Spectral Information from Logic NetlistsRolf Drechsler, Mitchell A. Thornton. 53-58 [doi]
• Fault Analysis of the Multiple Valued Logic Using Spectral MethodJong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim. 59 [doi]
• Neural Networks: Binary Monotonic and Multiple-ValuedJacek M. Zurada. 67 [doi]
• Data Mining of Weak Functional DecompositionsSzymon Jaroszewicz, Dan A. Simovici. 77-82 [doi]
• Some Properties of Discrete Interval Truth Valued LogicNoboru Takagi, Kyoichi Nakashima. 101-106 [doi]
• On Urquhart s C LogicAgata Ciabattoni. 113 [doi]
• A New Class of Fuzzy ModifiersMartine De Cock, Etienne E. Kerre. 121-126 [doi]
• Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule BasesKarsten Strehl, Claudio Moraga, Karl-Heinz Temme, Radomir S. Stankovic. 127-132 [doi]
• On Algebraic Foundations of Information Granulation III Investigating the HATA-MUKAIDONO ApproachHelmut Thiele. 133 [doi]
• Experiments on FPRM Expressions for Partially Symmetric Logic FunctionsSvetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko. 141-146 [doi]
• Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision DiagramsHafiz Md. Hasan Babu, Tsutomu Sasao. 147-152 [doi]
• A New Algorithm to Compute Quaternary Reed-Muller ExpansionsSusanto Rahardja, Bogdan J. Falkowski. 153 [doi]
• Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space SystemsAdrian Stoica. 161 [doi]
• De Morgan BisemilatticesJanusz A. Brzozowski. 173-178 [doi]
• Finite-Valued Approximations of Product LogicStefano Aguzzoli, Brunella Gerla. 179-184 [doi]
• Integration of Information in Four-Valued Logics under Non-Uniform AssumptionsYann Loyer, Nicolas Spyratos, Daniel Stamate. 185 [doi]
• Lower Bound Sifting for MDDsDragan Jankovic, Wolfgang Günther, Rolf Drechsler. 193-198 [doi]
• Fibonacci Decision Diagrams and Spectral Fibonacci Decision DiagramsRadomir S. Stankovic, Milena Stankovic, Jaakko Astola, Karen Egiazarian. 206 [doi]
• Cost-Analysis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS CircuitsMostafa H. Abd-El-Barr, Abdullah Al-Mutawa. 215-220 [doi]
• Implementation of Multiple-Valued Multiplier on GF(3m) Using Current Mode CMOSHyeon Kyeong Seong, Jai Seok Choi, Boo Sik Shin, Heung-Soo Kim. 221-226 [doi]
• Novel ?-Type Resistor Network in D/A Converter Based on Multiple-Valued LogicXunwei Wu, XuanChang Zhou. 227 [doi]
• Dynamic Re-Encoding During MDD MinimizationFrank Schmiedle, Wolfgang Günther, Rolf Drechsler. 239-244 [doi]
• Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-AlgorithmNaotake Kamiura, Yutaka Hata, Nobuyuki Matsui. 245 [doi]
• Evolutionary Multi-Level Network Synthesis in Given Design StyleTadeusz Luba, Claudio Moraga, Svetlana N. Yanushkevich, M. Opoka, Vlad P. Shmerko. 253-258 [doi]
• An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic OperationsTakahiro Hozumi, Osamu Kakusho, Kazuharu Yamato. 259-264 [doi]
• Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4)Svetlana N. Yanushkevich, Denis V. Popel, Vlad P. Shmerko, V. Cheushev, Radomir S. Stankovic. 265 [doi]
• On an Architecture of Medical Image Registration System Based on Multiple-Valued LogicYutaka Hata, Syoji Kobashi, Naotake Kamiura, Yuri T. Kitamura, Toshio Yanagida. 273-278 [doi]
• A Four-Valued Logic B(4) of E(9) for Modeling Human CommunicationDavid Rine, Raiek Alnakari. 285 [doi]
• Structures with Many-Valued Information and Their Relational Proof TheoryIvo Düntsch, Wendy MacCaull, Ewa Orlowska. 293 [doi]
• Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-FlopTetsuya Uemura, Toshio Baba. 305-310 [doi]
• A Study on the Ternary Parallel Circuit Design with DCG Properties Based on the Matrix EquationGi-Noung Byun, Chol-U Lee, Seung-Yong Park, Heung-Soo Kim. 311-316 [doi]
• Novel Resonant-Tunneling Multiple-Threshold Logic Circuit Based on Switching Sequence DetectionTakao Waho, Kazufumi Hattori, Kouji Honda. 317-322 [doi]
• Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance DevicesAlejandro F. González, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder. 323 [doi]
• The 2-SAT Problem of Regular Signed CNF FormulasBernhard Beckert, Reiner Hähnle, Felip Manyà. 331-336 [doi]
• Chaining Techniques for Automated Theorem Proving in Many-Valued LogicsHarald Ganzinger, Viorica Sofronie-Stokkermans. 337-344 [doi]
• High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection TablesTakafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi. 345 [doi]
• Properties of Independent Components of Self-Motion Optical FlowMarwan A. Jabri, Ki-Young Park, Soo-Young Lee, Terrence J. Sejnowski. 355 [doi]
• A Multilevel-Cell 32MB Flash MemoryM. Bauer, R. Alexis, Greg Atwood, B. Baltar, Al Fazio, K. Frary, M. Hensel, M. Ishac, J. Javanifard, M. Landgraf, D. Leak, K. Loe, Duane Mills, P. Ruby, R. Rozman, S. Sweha, S. Talreja, K. Wojciechowski. 367 [doi]
• Hardware Implementation of Supplementary Symmetrical Logic Circuit Structure ConceptsDan Olson, K. Wayne Current. 371-376 [doi]
• Design of a Quaternary Latch Circuit Using a Binary CMOS RS LatchK. Wayne Current. 377-381 [doi]
• Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal LevelsTakahiro Hanyu, Tsukasa Ike, Michitaka Kameyama. 382 [doi]
• Rigidity Problem of Autodual ClonesMasahiro Miyakawa, Ivo G. Rosenberg. 391-395 [doi]
• On the Intersection of Maximal Partial Clones and the Join of Minimal Partial ClonesLucien Haddad, Hajime Machida, Ivo G. Rosenberg. 396-401 [doi]
• Logic Synthesis of Controllers for B-Ternary Asynchronous SystemsYasunori Nagata, D. Michael Miller, Masao Mukaidono. 402 [doi]
• Silicon Single-Electron Devices and Their ApplicationsYasuo Takahashi, Akira Fujiwara, Yukinori Ono, Katsumi Murase. 411 [doi]
• DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge StorageTakahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama. 423-429 [doi]
• An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple AccessYasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi. 430-437 [doi]
• Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode LogicShunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama. 438 [doi]
• A Method for Approximate Equivalence CheckingMitchell A. Thornton, Rolf Drechsler, Wolfgang Günther. 447-452 [doi]
• Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued LogicXunwei Wu, Massoud Pedram. 453-459 [doi]