Table of Contents

• Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with MooreValeriu Beiu. [doi]
• The Ternary Calculating Machine of Thomas FowlerMark Glusker. [doi]
• Automated Reasoning in Some Local Extensions of Ordered StructuresViorica Sofronie-Stokkermans, Carsten Ihlemann. 1 [doi]
• Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition RuleRadomir S. Stankovic, Jaakko Astola. 2 [doi]
• Model-Characterizing Formulas and Normal Forms in Godel LogicsHeng Zhang, Mingyi Zhang. 3 [doi]
• Spectral Analysis of Special Properties of Ternary FunctionsClaudio Moraga, Milena Stankovic, Suzana Stojkovic. 4 [doi]
• Representations of Elementary Functions Using Edge-Valued MDDsShinobu Nagayama, Tsutomu Sasao. 5 [doi]
• Experimental Studies on SAT-Based ATPG for Gate Delay FaultsStephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel. 6 [doi]
• Polynomials as Generators of Minimal ClonesHajime Machida, Michael Pinsker. 7 [doi]
• Restriction-Closed HyperclonesB. A. Romov. 8 [doi]
• Monoidal Intervals of Partial ClonesLucien Haddad, Hajime Machida, Ivo G. Rosenberg. 9 [doi]
• Variable Reordering and Sifting for QMDDD. Michael Miller, David Y. Feinstein, Mitchell A. Thornton. 10 [doi]
• GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic CircuitsMozammel H. A. Khan, Marek A. Perkowski. 11 [doi]
• A Generalization of the Deutsch-Jozsa Algorithm to Multi-Valued Quantum LogicYale Fan. 12 [doi]
• The Genetic Code as a Multiple-Valued Function and Its Implementation Using Multilayer Neural Network Based on Multi-Valued NeuronsIgor N. Aizenberg, Claudio Moraga. 13 [doi]
• Non-deterministic Multi-valued Matrices for First-Order Logics of Formal InconsistencyArnon Avron, Anna Zamansky. 14 [doi]
• New Fastest Linearly Independent Transforms over GF(3)Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba. 15 [doi]
• Inversion/Division in Galois Field Using Multiple-Valued LogicNabil Abu-Khader, Pepe Siy. 16 [doi]
• Boolean Functions of Low Polynomial Degree for Quantum Query Complexity TheoryRusins Freivalds, Liva Garkaje. 17 [doi]
• Quantum Robots for TeenagersArushi Raghuvanshi, Yale Fan, Michal Woyke, Marek A. Perkowski. 18 [doi]
• Quantum Mechanical Model of Emotional Robot BehaviorsMartin Lukac, Marek A. Perkowski. 19 [doi]
• Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud GatesAsif I. Khan, Nadia Nusrat, Samira M. Khan, Masud Hasan, Mozammel H. A. Khan. 20 [doi]
• 2-SAT Problems in Some Multi-Valued Logics Based on Finite LatticesWitold Charatonik, Michal Wrona. 21 [doi]
• A Complete Resolution Calculus for Signed Max-SATCarlos Ansótegui, Maria Luisa Bonet, Jordi Levy, Felip Manyà. 22 [doi]
• Efficient Algorithm for Calculation of Quaternardy Fixed Polarity Arithmetic ExpansionsBogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba. 23 [doi]
• Multiple-Valued Logic Circuits Design Using Negative Differential Resistance DevicesKrzysztof S. Berezowski, Sarma B. K. Vrudhula. 24 [doi]
• Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair CircuitsNobuaki Okada, Michitaka Kameyama. 25 [doi]
• Equalization Techniques for Multiple-Valued Data Transmission and Their ApplicationYasushi Yuminaka, Kazuyoshi Yamamura. 26 [doi]
• The Rough Powerset MonadPatrik Eklund, Maria A. Galán. 27 [doi]
• Exploiting Homogeneous Dual Polarity Routes in Implementation of Algorithms for Optimization of Galois Field Expressions for Ternary FunctionsDragan Jankovic, Radomir S. Stankovic, Claudio Moraga. 28 [doi]
• Automated Reasoning Algorithm for Linguistic Valued Lukasiewicz Propositional LogicJun Liu, Luis Martinez Lopez, Yang Xu, Zhirui Lu. 29 [doi]
• Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate DevicesHenning Gundersen, Yngvar Berg. 30 [doi]
• Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree DiagramsNaofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi. 31 [doi]
• On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. 32 [doi]
• On the Axiomatization of Generalized Entropic MetricsDan A. Simovici. 33 [doi]
• Characterization of Partial Sheffer Functions in 3-Valued LogicLucien Haddad, Dietlinde Lau. 34 [doi]
• Power Indexes in Voting Systems and Multiple-Valued LogicYoshinori Yamamoto. 35 [doi]
• A Ternary Analog-to-Digital Converter SystemTomoki Tanoue, Munehiko Nagatani, Takao Waho. 36 [doi]
• Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate DevicesRenè Jensen, Yngvar Berg. 37 [doi]
• Fault Tolerant CMOS Logic Using Ternary GatesYngvar Berg, Renè Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet. 38 [doi]
• Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic OperationTasuku Ito, Michitaka Kameyama. 39 [doi]
• An Application of 16-Valued Logic to Design of Reconfigurable Logic ArraysTsutomu Sasao. 40 [doi]
• Linearization of Ternary Decision Diagrams by Using the Polynomial Chrestenson SpectrumMilena Stankovic, Suzana Stojkovic, Claudio Moraga. 41 [doi]
• Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemCAndré Sülflow, Rolf Drechsler. 42 [doi]
• Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD ProcessorHirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto. 43 [doi]
• Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling SchemeTomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu. 44 [doi]
• Classifications and Enumeration of Bases in P_{3}(2)Dietlinde Lau, Masahiro Miyakawa. 45 [doi]
• Simulation of Gate Circuits with Feedback in Multi-Valued AlgebrasJanusz A. Brzozowski, Yuli Ye. 46 [doi]
• Properties and Fast Algorithms for Ternary Walsh TransformBogdan J. Falkowski, Shixing Yan. 47 [doi]
• Weighted and Ordered Direct Cover Algorithms for Minimization of MVL FunctionsMostafa Abd-El-Barr, Bambang A. B. Sarif. 48 [doi]
• Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel JunctionsTetsuya Uemura, T. Marukame, K.-i. Matsuda, Masafumi Yamamoto. 49 [doi]
• Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDLMahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler. 50 [doi]
• Limits to a Correct Evaluation in RTD-Based Quaternary InvertersJuan Núñez, José M. Quintana, Maria J. Avedillo. 51 [doi]
• Evaluation and Comparison of Threshold Logic GatesVasilios Lirigis, Elena Dubrova. 52 [doi]
• Towards First-Order Symbolic Trajectory EvaluationDonglin Li, Otmane Aït Mohamed, Sa ed Abed. 53 [doi]
• Survey of Stochastic Computation on Factor GraphsSaeed Sharifi Tehrani, Shie Mannor, Warren J. Gross. 54 [doi]
• A Note on Possible Applications of Fourier Representations in Circuit Design over Reprogrammable Technological PlatformsRadomir S. Stankovic, Jaakko Astola. 55 [doi]
• Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic DesignRicardo Cunha, Henri Boudinov, Luigi Carro. 56 [doi]
• High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise ReductionAkira Mochizuki, Masatomo Miura, Takahiro Hanyu. 57 [doi]
• Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon ProcessMotoi Inaba. 58 [doi]