Abstract is missing.
- The big pileupNick Mitchell. 1 [doi]
- Dynamic program analysis of Microsoft Windows applicationsAlex Skaletsky, Tevi Devor, Nadav Chachmon, Robert S. Cohn, Kim M. Hazelwood, Vladimir Vladimirov, Moshe Bach. 2-12 [doi]
- LagAlyzer: A latency profile analysis and visualization toolAndrea Adamoli, Milan Jovic, Matthias Hauswirth. 13-22 [doi]
- Characterizing the design and performance of interactive java applicationsDmitrijs Zaparanuks, Matthias Hauswirth. 23-32 [doi]
- Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloadsKarthik Ganesan, Jungho Jo, Lizy K. John. 33-44 [doi]
- ArchExplorer.org: A methodology for facilitating a fair Comparison of research ideasVeerle Desmet, Sylvain Girbal, Olivier Temam. 45-54 [doi]
- StatStack: Efficient modeling of LRU cachesDavid Eklov, Erik Hagersten. 55-65 [doi]
- Modeling memory concurrency for multi-socket multi-core systemsAnirban Mandal, Rob Fowler, Allan Porterfield. 66-75 [doi]
- Cache contention and application performance prediction for multi-core systemsChi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley Mao. 76-86 [doi]
- Memphis: Finding and fixing NUMA-related performance problems on multi-core platformsCollin McCurdy, Jeffrey S. Vetter. 87-96 [doi]
- Understanding transactional memory performanceDonald E. Porter, Emmett Witchel. 97-108 [doi]
- Influences of SIMD architectures for scattered data interpolation algorithmJean-Charles Tournier, Martin Naef. 109-110 [doi]
- Hardware prediction of OS run-length for fine-grained resource customizationDavid Nellans, Kshitij Sudan, Rajeev Balasubramonian, Erik Brunvand. 111-112 [doi]
- Program behavior characterization in large memory systemsParijat Dube, Michael Tsao, Dan E. Poff, Li Zhang, Alan Bivens. 113-114 [doi]
- Simulation environment for studying overlap of communication and computationVladimir Subotic, Jesús Labarta, Mateo Valero. 115-116 [doi]
- Scalability comparison of commodity operating systems on multi-coresYan Cui, Yu Chen, Yuanchun Shi, Qingbo Wu. 117-118 [doi]
- Incorporating Instruction-Based Sampling into AMD CodeAnalystPaul J. Drongowski, Lei Yu, Frank Swehosky, Suravee Suthikulpanit, Robert Richter. 119-120 [doi]
- Using special-purpose hardware to achieve a hundred-fold speedup in molecular dynamics simulations of proteinsDavid Shaw. 121 [doi]
- The Hadoop distributed filesystem: Balancing portability and performanceJeffrey Shafer, Scott Rixner, Alan L. Cox. 122-133 [doi]
- Scaling OLTP applications on commodity multi-core platformsYan Cui, Yu Chen, Yuanchun Shi. 134-143 [doi]
- A study of hardware assisted IP over InfiniBand and its impact on enterprise data center performanceRyan E. Grant, Pavan Balaji, Ahmad Afsahi. 144-153 [doi]
- Weak execution ordering - exploiting iterative methods on many-core GPUsJianmin Chen, Zhuo Huang, Feiqi Su, Jih-Kwon Peir, Jeff Ho, Lu Peng. 154-163 [doi]
- Visualizing complex dynamics in many-core accelerator architecturesAaron Ariel, Wilson W. L. Fung, Andrew E. Turner, Tor M. Aamodt. 164-174 [doi]
- PEBIL: Efficient static binary instrumentation for LinuxMichael Laurenzano, Mustafa M. Tikir, Laura Carrington, Allan Snavely. 175-183 [doi]
- High-level performance modeling of task-based algorithmsAlexei Alexandrov, Douglas Armstrong, Hrabri Rajic, Michael Voss, Donald Hayes. 184-193 [doi]
- Exploiting FPGAs for technology-aware system-level evaluation of multi-core architecturesSimone Secchi, Paolo Meloni, Luigi Raffo. 194-202 [doi]
- Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessorHarold W. Cain, Priya Nagpurkar. 203-212 [doi]
- An analysis of hard to predict branchesCelal Ozturk, Resit Sendag. 213-222 [doi]
- Performance-effective operation below Vcc-minNikolas Ladas, Yiannakis Sazeides, Veerle Desmet. 223-234 [doi]
- Demystifying GPU microarchitecture through microbenchmarkingHenry Wong, Misel-Myrto Papadopoulou, Maryam Sadooghi-Alvandi, Andreas Moshovos. 235-246 [doi]