Abstract is missing.
- Keynote I: The era of heterogeneity: Are we prepared?Ravishankar Iyer. 1 [doi]
- Characterization and dynamic mitigation of intra-application cache interferenceCarole-Jean Wu, Margaret Martonosi. 2-11 [doi]
- A semi-preemptive garbage collector for solid state drivesJungHee Lee, Youngjae Kim, Galen M. Shipman, Sarp Oral, Feiyi Wang, Jongman Kim. 12-21 [doi]
- PRISM: Zooming in persistent RAM storage behaviorJu-Young Jung, Sangyeun Cho. 22-31 [doi]
- Evaluation and optimization of multicore performance bottlenecks in supercomputing applicationsJeffrey R. Diamond, Martin Burtscher, John D. McCalpin, Byoung-Do Kim, Stephen W. Keckler, James C. Browne. 32-43 [doi]
- Minimizing interference through application mapping in multi-level buffer cachesChristina M. Patrick, Nicholas Voshell, Mahmut T. Kandemir. 44-55 [doi]
- Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memorySantiago Bock, Bruce R. Childers, Rami G. Melhem, Daniel Mossé, Youtao Zhang. 56-65 [doi]
- Memory access pattern-aware DRAM performance model for multi-core systemsHyojin Choi, Jongbok Lee, Wonyong Sung. 66-75 [doi]
- Characterizing multi-threaded applications based on shared-resource contentionTanima Dey, Wei Wang, Jack W. Davidson, Mary Lou Soffa. 76-86 [doi]
- Trace-driven simulation of multithreaded applicationsAlejandro Rico, Alejandro Duran, Felipe Cabarcas, Yoav Etsion, Alex RamÃrez, Mateo Valero. 87-96 [doi]
- Efficient memory tracing by program skeletonizationAlain Ketterlin, Philippe Clauss. 97-106 [doi]
- Portable trace compression through instruction interpretationSvilen Kanev, Robert Cohn. 107-116 [doi]
- Finding cool code: An analysis of source-level causes of temperature effectsDan Upton, Kim M. Hazelwood. 117-118 [doi]
- A reconfigurable simulator for large-scale heterogeneous multicore architecturesJiayuan Meng, Kevin Skadron. 119-120 [doi]
- Towards a scalable data center-level evaluation methodologyDavid Meisner, Junjie Wu, Thomas F. Wenisch. 121-122 [doi]
- Storage I/O generation and replay for datacenter applicationsChristina Delimitrou, Sriram Sankar, Kushagra Vaid, Christos Kozyrakis. 123-124 [doi]
- VMAD: A virtual machine for advanced dynamic analysis of programsAlexandra Jimborean, Matthieu Herrmann, Vincent Loechner, Philippe Clauss. 125-126 [doi]
- A comparative benchmarking of the FFT on Fermi and Evergreen GPUsMohamed F. Ahmed, Omar Haridy. 127-128 [doi]
- Supply voltage emulation platform for DVFS voltage drop compensation explorationsAndreas Genser, Christian Bachmann, Christian Steger, Reinhold Weiss, Josef Haid. 129-130 [doi]
- Performance characterization of mobile-class nodes: Why fewer bits is betterMichelle McDaniel, Kim M. Hazelwood. 131-132 [doi]
- Keynote II: Integrated modeling challenges in extreme-scale computingPradip Bose. 133 [doi]
- Where is the data? Why you cannot debate CPU vs. GPU performance without the answerChris Gregg, Kim M. Hazelwood. 134-144 [doi]
- Accelerating search and recognition workloads with SSE 4.2 string and text processing instructionsGuangyu Shi, Min Li, Mikko H. Lipasti. 145-153 [doi]
- A comprehensive analysis and parallelization of an image retrieval algorithmZhenman Fang, Donglei Yang, Weihua Zhang, Haibo Chen, Binyu Zang. 154-164 [doi]
- Performance evaluation of adaptivity in software transactional memoryMathias Payer, Thomas R. Gross. 165-174 [doi]
- Scalable, accurate multicore simulation in the 1000-core eraMieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas. 175-185 [doi]
- A single-specification principle for functional-to-timing simulator interface designDavid A. Penry. 186-196 [doi]
- WiLIS: Architectural modeling of wireless systemsKermin Elliott Fleming, Man Cheuk Ng, Samuel Gross, Arvind. 197-206 [doi]
- Detecting race conditions in asynchronous DMA operations with full system simulationMichael Kistler, Daniel A. Brokenshire. 207-215 [doi]
- Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardwareStijn Eyerman, Kenneth Hoste, Lieven Eeckhout. 216-226 [doi]
- Power signature analysis of the SPECpower_ssj2008 benchmarkChung-Hsing Hsu, Stephen W. Poole. 227-236 [doi]
- Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variationJungseob Lee, Paritosh Pratap Ajgaonkar, Nam Sung Kim. 237-246 [doi]
- Universal rules guided design parameter selection for soft error resilient processorsLide Duan, Ying Zhang, Bin Li, Lu Peng. 247-256 [doi]
- A dynamic energy management scheme for multi-tier data centersSeung-Hwan Lim, Bikash Sharma, Byung-Chul Tak, Chita R. Das. 257-266 [doi]