Abstract is missing.
- Physical design of biological systemsLouis Scheffer. 1 [doi]
- Going with the flow: bridging the gap between theory and practice in physical designPatrick Groeneveld. 3 [doi]
- Design planning trends and challengesNeeraj Kaul. 5 [doi]
- What makes a design difficult to routeCharles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo Tellez. 7-12 [doi]
- Physical design challenges beyond the 22nm nodeSani R. Nassif, Kevin J. Nowka. 13-14 [doi]
- Challenges and opportunities in optimization of automotive electronicsSerge Leef. 15 [doi]
- Thinking outside of the chipJohn Park. 17 [doi]
- B-escape: a simultaneous escape routing algorithm based on boundary routingLijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya. 19-25 [doi]
- FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree constructionGaurav Ajwani, Chris Chu, Wai-Kei Mak. 27-34 [doi]
- Completing high-quality global routesJin Hu, Jarrod A. Roy, Igor L. Markov. 35-41 [doi]
- Analog layout synthesis: what s missing?Rob A. Rutenbar. 43 [doi]
- Design platform for electrical and physical co-design of analog circuitsMar Hershenson. 45 [doi]
- Automatic generation of hierarchical placement rules for analog integrated circuitsMichael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann. 47-54 [doi]
- Adding a new dimension to physical designSachin S. Sapatnekar. 55 [doi]
- Physical design implementation for 3D IC: methodology and toolsVassilios Gerousis. 57 [doi]
- Efficient design practices for thermal management of a TSV based 3D IC systemZongwu Tang. 59 [doi]
- An analytical placer for mixed-size 3D placementJason Cong, Guojie Luo. 61-66 [doi]
- Logical and physical restructuring of fan-in treesHua Xiang, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho. 67-74 [doi]
- Ultra-fast interconnect driven cell cloning for minimizing critical path delayZhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Ying Zhou. 75-82 [doi]
- ITOP: integrating timing optimization within placementNatarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu. 83-90 [doi]
- Physical synthesis of bus matrix for high bandwidth low power on-chip communicationsRenshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng. 91-96 [doi]
- Dummy fill optimization for enhanced manufacturabilityYaoguang Wei, Sachin S. Sapatnekar. 97-104 [doi]
- Density gradient minimization with coupling-constrained dummy fill for CMP controlHuang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang. 105-111 [doi]
- Total sensitivity based dfm optimization of standard library cellsYongchan Ban, Savithri Sundareswaran, David Z. Pan. 113-120 [doi]
- A matching based decomposer for double patterning lithographyYue Xu, Chris Chu. 121-126 [doi]
- Skew management of NBTI impacted gated clock treesAshutosh Chakraborty, David Z. Pan. 127-133 [doi]
- Accurate clock mesh sizing via sequential quadraticprogrammingVenkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li. 135-142 [doi]
- ISPD 2010 high performance clock network synthesis contest: benchmark suite and resultsC. N. Sze. 143 [doi]
- Impact of local interconnects on timing and power in a high performance microprocessorRupesh S. Shelar, Marek Patyra. 145-152 [doi]
- Interconnect power and delay optimization by dynamic programming in gridded design rulesKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. 153-160 [doi]
- Performance study of VeSFET-based, high-density regular circuitsYi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly. 161-168 [doi]
- A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systemsYufu Zhang, Bing Shi, Ankur Srivastava. 169-176 [doi]
- Optimal wiring topology for electromigration avoidance considering multiple layers and obstaclesIris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang. 177-184 [doi]
- SafeChoice: a novel clustering algorithm for wirelength-driven placementJackey Z. Yan, Chris Chu, Wai-Kei Mak. 185-192 [doi]
- Droplet-routing-aware module placement for cross-referencing biochipsZigang Xiao, Evangeline F. Y. Young. 193-199 [doi]
- A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochipsTsung-Wei Huang, Tsung-Yi Ho. 201-208 [doi]