Table of Contents

• How Do You Select A High Quality EDA Tool Flow?Robert N. Blair, Jacques Benkoski. 17 [doi]
• Slap it Together and Ship it!Aart J. de Geus. 23-24 [doi]
• The Practical Side of QualityJohn East. 25-26 [doi]
• Design for Quality and ManufacturingPrakash Agrawal. 27-28 [doi]
• Ramping New IC Products in the Deep Submicron AgeJohn Kibarian. 29 [doi]
• What is Design Quality? How can Quality in Electronic Design be Quantified?Michael Reinhardt, Michael Santarini. 31 [doi]
• Transistor Modeling for the VDSM EraMichael S. Shur, Tor A. Fjeldly, Trond Ytterdal. 37-44 [doi]
• A Statistical Model for Electromigration FailuresGilbert Yoh, Farid N. Najm. 45-50 [doi]
• An Analytical Model for Delay and Crosstalk Estimation with Application to DecouplingMurat R. Becer, Ibrahim N. Hajj. 51-58 [doi]
• Power Macromodeling for a High Quality RT-Level Power EstimationRoberto Zafalon, Massimo Rossello, Enrico Macii, Massimo Poncino. 59 [doi]
• Overview of SiGe Technology Modeling and ApplicationJiann S. Yuan. 67-72 [doi]
• GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI DesignLifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami. 73-80 [doi]
• An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASICJi-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyung-Woo Kim, Sun-Il Yoo. 81-86 [doi]
• Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET sKwan-Do Kim, Young-Kwan Park, Jun-Ha Lee, Jeong-Taek Kong, Hee-Sung Kang, Young-Wug Kim, Seok-Jin Kim. 87 [doi]
• Quality-Driven System-on-a-Chip DesignLech Józwiak. 93 [doi]
• Measuring Design Quality by Measuring Design ComplexityMichael Keating. 103 [doi]
• Quality Memory Blocks -- Balancing the Trade-OffsBetty Prince. 109-114 [doi]
• Should Yield be a Design Objective?Israel Koren. 115-120 [doi]
• Early Addressing IC and Package Relationship Allows an Overall Better Quality of Complex SOCAnna Fontanelli, Luigi Arnone, Roberto Branca, Giorgio Mastrorocco. 121 [doi]
• LEMINGS: LSI s EMI-Noise Analysis with Gate Level SimulatorKenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano. 129-136 [doi]
• Dynamic Timing Analysis Considering Power Supply Noise EffectsYi-Min Jiang, Angela Krstic, Kwang-Ting Cheng. 137-144 [doi]
• Full Chip Thermal SimulationZhiping Yu, Dan Yergeau, Robert W. Dutton, O. Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie. 145-150 [doi]
• Enabling DIR(Designing-In-Reliability) through CAD CapabilitiesWonjae L. Kang, Brad Potts, Ray Hokinson, John Riley, David Doman, Frank Cano, N. S. Nagaraj, Noel Durrant. 151-156 [doi]
• Noise Safety Design MethodologiesMariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. 157 [doi]
• Design for Testability in Nanometer Technologies; Searching for QualityThomas W. Williams, Rohit Kapur. 167-172 [doi]
• Low Power Testing of VLSI Circuits: Problems and SolutionsPatrick Girard. 173-180 [doi]
• On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control TechniquesZhanping Chen, Liqiong Wei, Kaushik Roy. 181-188 [doi]
• Efficient Hierarchical Approach to Test Generation for Digital SystemsRaimund Ubar, Jaan Raik. 189-196 [doi]
• Quality of Electronic Design: From Architectural Level to Test CoverageOctávio Páscoa Dias, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 197 [doi]
• The Hidden Costs of Design QualitRichard Goering, Richard Wallace. 203 [doi]
• Platform-Based Design: A Path to Efficient Design Re-UseAlberto L. Sangiovanni-Vincentelli. 209-210 [doi]
• Embedded-Quality for TestYervant Zorian. 211-212 [doi]
• Deep Submicron USLI Design Paradigm: Who is Writing the Future?Kamran Eshraghian. 213 [doi]
• Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and MegacellsTomás Bautista, Antonio Núñez. 217-226 [doi]
• An Objective Measure of Digital System Design QualityDave Protheroe, Francesco Pessolano. 227-233 [doi]
• Achieving the Quality of Verification for Behavioral Models with Minimum EffortTom Chen, Anneliese Amschler Andrews, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu. 234 [doi]
• Extending Moore s Law through Advances in Semiconductor Manufacturing EquipmentAshok K. Sinha. 243-244 [doi]
• Combining Advanced Process Technology and Design for Systems Level IntegrationAna Hunter, C. K. Lau, John Martin. 245-250 [doi]
• ESD: Design For IC Chip Quality and ReliabilityCharvaka Duvvury. 251 [doi]
• Power Bus Maximum Voltage Drop in Digital VLSI CircuitsGeng Bai, Sudhakar Bobba, Ibrahim N. Hajj. 263-268 [doi]
• A Reliable Clock Tree Design Methodology for ASIC DesignsMely Chen Chi, Shih-Hsu Huang. 269-274 [doi]
• Fixing Antenna Problem by Dynamic Diode Dropping and Jumper InsertionPeter H. Chen, Sunil Malkani, Chun-Mou Peng, James Lin. 275-282 [doi]
• Project Management for System-on-Chip Using Multi-Chip ModulesDonald J. Dent. 283-290 [doi]
• A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog CircuitsMohamed Dessouky, Marie-Minerve Louërat. 291-298 [doi]
• On Testability of Multiple Precharged Domino LogicTh. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou. 299-304 [doi]
• DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan PathMakoto Ikeda, Hideyuki Aoki, Kunihiro Asada. 305-308 [doi]
• EMI Common-Mode Current Dependence on Delay Skew Imbalance in High Speed Differential Transmission Lines Operating at 1 Gigabit/second Data RatesJ. L. Knighten, N. W. Smith, L. O. Hoeft, J. T. DiBene II. 309-314 [doi]
• Internet-Based Virtual Manufacturing: A Verification Tool for IC DesignsWieslaw Kuzmicz. 315-320 [doi]
• A Reconfigurable Low-Power High-Performance Matrix Multiplier DesignRong Lin. 321-328 [doi]
• Electrical Characterization of Signal Routability and PerformanceMehdi M. Mechaik. 329-336 [doi]
• Full-Chip Signal Interconnect Analysis for Electromigration ReliabilitySteffen Rochel, N. S. Nagaraj. 337-340 [doi]
• Correct-by-Design CAD Enhancement for EMI Signal IntegrityErik A. McShane, Krishna Shenai. 341-346 [doi]
• A Transition Based BIST Approach for Passive Analog CircuitsAlvernon Walker, Parag K. Lala. 347-354 [doi]
• Aliasing-Free Space and Time Compactions with Limited OverheadJin Ding, David Moloney, Xiaojun Wang. 355-360 [doi]
• A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis QualityMatthew Worsman, Mike W. T. Wong, Y. S. Lee. 361-368 [doi]
• An Automated Shielding Algorithm and Tool For Dynamic CircuitsGin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen. 369-374 [doi]
• A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect ImpedanceLi-Fu Chang, Keh-Jeng Chang, Christophe J. Bianchi. 375-378 [doi]
• Applying the OpenMORE Assessment Program for IP CoresJean-Pierre Gukguen, Pierre Bricaud. 379 [doi]
• Focus on Quality of Design: Does it Help or Hinder Time to Market?Nader Vasseghi, Rita Glover. 383 [doi]
• Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design ExperiencesEinar J. Aas. 389-394 [doi]
• Quality of EDA CAD Tools: Definitions, Metrics and DirectionsAmir H. Farrahi, David J. Hathaway, Maogang Wang, Majid Sarrafzadeh. 395-406 [doi]
• Tool Interoperability is Key to Improved Design QualityRichard Goldman, Karen Bartleson. 407 [doi]
• Advancing Customer-Perceived Quality in the EDA IndustryGiora Ben-Yaacov, Larry Bjork, Edward P. Stone. 411 [doi]
• Reducing Power Consumption of CMOS VLSI s through VDD and VTH ControlTakayasu Sakurai. 417-424 [doi]
• Peak Power Reduction in Low Power BISTXiaodong Zhang, Kaushik Roy. 425-432 [doi]
• Low Power BIST for Wallace Tree-Based Fast MultipliersDimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos. 433-438 [doi]
• Probabilistic Bottom-Up RTL Power EstimationRicardo Ferreira, A.-M. Trullemans, José C. Costa, José Monteiro. 439 [doi]
• Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead?Carlo Guardiani, Andrzej J. Strojwas. 447 [doi]
• Design for Variability in DSM TechnologiesSani R. Nassif. 451-454 [doi]
• Realistic Worst-Case Modeling by Performance Level Principal Component AnalysisAlessandra Nardi, Andrea Neviani, Carlo Guardiani. 455-460 [doi]
• Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI DesignsValery Axelrad, Nicolas B. Cobb, M. O Brien, Thuy Do, Tom Donnelly, Yuri Granik, Emile Y. Sahouria, Victor Boksha, Artur Balasinski. 461-466 [doi]
• Electronic Process Limited YieldGary W. Maier, Shawn Smith. 467-474 [doi]
• Effects of Package Stackups on Microprocessor PerformanceMehdi M. Mechaik. 475 [doi]
• Coupling Noise Analysis for VLIS and ULSI CircuitsKathirgamar Aingaran, Fabian Klass, Chin-Man Kim, Chaim Amir, Joydeep Mitra, Eileen You, Jamil Mohd, Sai-keung Dong. 485-490 [doi]
• Efficient Delay Calculation in Presence of CrosstalkTong Xiao, Malgorzata Marek-Sadowska. 491-498 [doi]
• Crosstalk Aware Static Timing Analysis: A Two Step ApproachBruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro. 499-504 [doi]
• Deep Sub-Micron Static Timing Analysis in Presence of CrosstalkPeivand F. Tehrani, Shang Woo Chyou, Uma Ekambaram. 505-512 [doi]
• Quick On-Chip Self- and Mutual-Inductance ScreenShen Lin, Norman Chang, O. Sam Nakagawa. 513 [doi]