Table of Contents

• Nanometer-Scale CMOS DevicesKerry Bernstein. 7 [doi]
• Interconnect ModelingJeff Davis. 7 [doi]
• Low-Power DesignKaushik Roy. 8 [doi]
• Manufacturability Andrew B. Kahng. 8 [doi]
• Coping with UncertaintyNagib Hakim. 9 [doi]
• Evening Panel Discussion: DFM PDK s: Where Do They Belong To? Are Process Design Kits (PDKs) the Answer for Modern Design for Manufacturing (DFM) Issues?Tets Maniwa, Pallab K. Chatterjee. 11-13 [doi]
• Simplify: Enable Quality, Enable InnovationJohn Chilton. 17 [doi]
• Design for Manufacturing? Design for Yield!!!Marc E. Levitt. 19 [doi]
• Why Nano Technology? Why Now? And What Might Its Impact on ElectronicsLarry Bock. 21 [doi]
• Calligrapher: A New Layout Migration Engine Based on Geometric ClosenessFang Fang, Jianwen Zhu. 25-30 [doi]
• Methodology for Automated Layout Migration for 90 nm Itanium®2 Processor DesignKuang-Kuo Lin, Sudhakar Kale, Aditi Nigam. 31-35 [doi]
• Automatic Generation of Standard Cell Library in VDSM TechnologiesMasanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera. 36-41 [doi]
• A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP ApproachJin He, Xuemei Xi, Mansun Chan, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu. 45-50 [doi]
• Leakage Increase of Narrow and Short BCPMOSY. Z. Xu, O. Pohland, C. Cai, H. Puchner. 51-54 [doi]
• SRAM Leakage Suppression by Minimizing Standby Supply VoltageHuifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey. 55-60 [doi]
• Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit ModelingZhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong. 63-68 [doi]
• Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power ReductionLucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He. 69-74 [doi]
• Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk NoiseHerng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng. 75-80 [doi]
• New Test Access for High Resolution SD ADC s by Using the Noise Transfer Function EvaluationDaniela De Venuto. 81-85 [doi]
• Design for Testability of FPGA BlocksStuart McCracken, Zeljko Zilic. 86-91 [doi]
• New Challenges Emerging on the Design of VLSI Circuits Made of MOSFETs Using New Gate Dielectric MaterialsNikos Konofaos, G. Ph. Alexiou. 92-97 [doi]
• Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned FloorplanDongku Kang, Mark C. Johnson, Kaushik Roy. 98-103 [doi]
• Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic CircuitsVolkan Kursun, Eby G. Friedman. 104-109 [doi]
• Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)110-115 [doi]
• Transistor Level Budgeting for Power OptimizationEren Kursun, Soheil Ghiasi, Majid Sarrafzadeh. 116-121 [doi]
• Resistance Matrix in Crosstalk Modeling for Muliconductor SystemsSunil Yu, Dusan Petranovic, Shoba Krishnan, Kwyro Lee, Cary Y. Yang. 122-125 [doi]
• Low Power 260 k Color TFT LCD One-Chip Driver ICBo-Sung Kim, Young-Gi Kim, Soon-Yang Hong. 126-130 [doi]
• Analysis and Reduction of On-Chip Inductance Effects in Power Supply GridsWoo Hyung Lee, Sanjay Pant, David Blaauw. 131-136 [doi]
• A Variable Reduction Technique for the Analysis of Ultra Large-Scale Power Distribution NetworksJong-Eun Koo, Kyung Ho Lee, Young-Hoe Cheon, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong. 137-142 [doi]
• Rewiring for Watermarking Digital CircuitsM. Moiz Khan, Spyros Tragoudas. 143-148 [doi]
• The IP Quality RevolutionMichael Keating. 151-155 [doi]
• Layout Printability Optimization Using a Silicon Simulation MethodologyMichel Côté, Philippe Hurat. 159-164 [doi]
• A Pattern Matching System for Linking TCAD and EDAFrank Gennari, Andrew R. Neureuther. 165-170 [doi]
• Shifting Methods: Adopting a Design for Manufacture FlowJohn Ferguson. 171-175 [doi]
• Design Tools for PackagingLalitha Immaneni, Anju Kapur, Brett Neal. 179-183 [doi]
• Robustness Enhancement through Chip-Package Co-Design for High-Speed ElectronicsMeigen Shen, Li-Rong Zheng, Hannu Tenhunen. 184-189 [doi]
• Flip Chip Advanced Package Solder Joint Embrittlement Fault Isolation Using TDRRoderick P. Cruz. 190-195 [doi]
• A Clustering Based Area I/O Planning for Flip-Chip TechnologyJanet Meiling Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar. 196-201 [doi]
• Low Power Testing by Test Vector Ordering with Vector RepetitionMaciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos. 205-210 [doi]
• Test Application Time Reduction for Scan Circuits Using Limited Scan OperationsYonsang Cho, Irith Pomeranz, Sudhakar M. Reddy. 211-216 [doi]
• Functional Vector Generation for Combinational Circuits Based on Data Path Coverage Metric and Mixed Integer Linear ProgrammingJ. Sosa, Juan A. Montiel-Nelson, Héctor Navarro, José C. García. 217-222 [doi]
• Physically-Based Simulation of Electromigration Induced Failures in Copper Dual-Damascene InterconnectValeriy Sukharev. 225-231 [doi]
• A Methodology for Chip-Level Electromigration Risk Assessment and Product QualificationChanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda. 232-237 [doi]
• Circuit Level Reliability Analysis of Cu InterconnectsSyed M. Alam, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel. 238-243 [doi]
• Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design FlowPavel V. Nikitin, Vikram Jandhyala, Daniel White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway. 244-249 [doi]
• A Divide-and-Conquer Algorithm for 3D Capacitance ExtractionFangqing Yu, Weiping Shi. 253-258 [doi]
• A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot ArrayAnirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee. 259-264 [doi]
• Interconnect Mode Conversion in High-Speed VLSI CircuitsY. Quéré, T. LeGouguec, P. M. Martin, F. Huret. 265-270 [doi]
• Efficient Capacitance Extraction for Periodic Structures by Shanks TransformationYe Liu, Mei Xue, Zheng-Fan Li, Rui-Feng Xue. 271-275 [doi]
• PARADE: PARAmetric Delay Evaluation under Process VariationXiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi. 276-280 [doi]
• Substrate Coupling: Modeling, Simulation and Design PerspectivesRanjit Gharpurey, Edoardo Charbon. 283-290 [doi]
• An Overview of Substrate Noise Reduction TechniquesShahab Ardalan, Manoj Sachdev. 291-296 [doi]
• Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory DesignsMeng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai. 297-302 [doi]
• Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC DesignGeorgios Veronis, Yi-Chang Lu, Robert W. Dutton. 303-308 [doi]
• Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary ApproachHenry H. Y. Chan, Zeljko Zilic. 309-314 [doi]
• Evening Panel Discussion: IP Industry: Nordstrom or K-Mart? The Trend Toward Tighter Relationships between Suppliers and UsersRon Wilson, Phil Dworsky. 317-319 [doi]
• Digitally Named World: Challenges for New Social InfrastructuresHiroto Yasuura. 323 [doi]
• Designing High Quality, Scaleable SoC??s with Heterogeneous ComponentsPierre G. Paulin. 325 [doi]
• Performance Limitations of Devices and Interconnects and Possible Alternatives for NanoelectronicsKrishna Saraswat. 327 [doi]
• A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled InterconnectsMedha Kulkarni, Tom Chen. 331-336 [doi]
• Analytical Dynamic Time Delay Model of Strongly Coupled RLC Interconnect Lines Dependent on SwitchingSeongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim. 337-342 [doi]
• A Scalable Communication-Centric SoC Interconnect ArchitectureCristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh. 343-348 [doi]
• Application Specific Worst Case Corners Using Response Surfaces and Statistical ModelsManidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, Jianjun Cheng. 351-356 [doi]
• SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order ReductionTing-Yuan Wang, Charlie Chung-Ping Chen. 357-362 [doi]
• Predicting Interconnect Uncertainty with a New Robust Model Order Reduction MethodJanet Meiling Wang, Omar Hafiz. 363-368 [doi]
• A High Performance SIMD Framework for Design Rule Checking on Sony??s PlayStation 2 Emotion Engine PlatformSandeep Koranne. 371-376 [doi]
• Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic CellsTetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. 377-380 [doi]
• Buffered Clock Tree for High Quality IC DesignRishi Chaturvedi, Jiang Hu. 381-386 [doi]
• Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply CurrentSwarup Bhunia, Arijit Raychowdhury, Kaushik Roy. 389-394 [doi]
• A Versatile High Speed Bit Error Rate Testing SchemeYongquan Fan, Zeljko Zilic, Man Wah Chiang. 395-400 [doi]
• Automated Test Generation and Test Point Selection for Specification Test of Analog CircuitsAchintya Halder, Abhijit Chatterjee. 401-406 [doi]
• Power Supply Optimization in sub-130 nm Leakage Dominant Technologies Man Lung Mui, Kaustav Banerjee, Amit Mehrotra. 409-414 [doi]
• Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS TechnologiesBhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy. 415-420 [doi]
• Low Power and High Performance Circuit Techniques for High Fan-In Dynamic GatesGe Yang, Zhongda Wang, Sung-Mo Kang. 421-424 [doi]
• Stacked FSMD: A Power Efficient Micro-Architecture for High Level SynthesisKhushwinder Jasrotia, Jianwen Zhu. 425-430 [doi]
• Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal LevelsMing-Dou Ker, Wei-Jen Chang, Wen-Yu Lo. 433-438 [doi]
• Full-Chip Analysis Method of ESD Protection NetworkSachio Hayashi, Fumihiro Minami, Masaaki Yamada. 439-444 [doi]
• Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS ProcessesMing-Dou Ker, Wen-Yi Chen. 445-450 [doi]
• Post Silicon Power/Performance Optimization in the Presence of ProcessVariations Using Individual Well Adaptive Body Biasing (IWABB)Justin Gregg, Tom W. Chen. 453-458 [doi]
• Concurrent Error Detection for Combinational and Sequential Logic via Output CompactionSobeeh Almukhaizim, Petros Drineas, Yiorgos Makris. 459-464 [doi]
• Cost Model Analysis of DFT Based Fault Tolerant SOC DesignsKarthik Sundararaman, Shambhu J. Upadhyaya, Martin Margala. 465-469 [doi]
• Managing Derivative SoC Design Projects to Better ResultsLane Albanese. 470-477 [doi]
• IPQ: IP Qualification for Efficient System DesignHans-Jürgen Brand, Steffen Rülke, Martin Radetzki. 478-482 [doi]
• Delay Fault Diagnosis Using Timing InformationZhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. 485-490 [doi]
• An Adaptive Path Delay Fault Diagnosis MethodologySaravanan Padmanaban, Spyros Tragoudas. 491-496 [doi]
• Scan BIST Targeting Transition Faults Using a Markov SourceHangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy. 497-502 [doi]
• The Effect of Threshold Voltages on the Soft Error RateVijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. 503-508 [doi]
• FinFET SRAM - Device and Circuit Design ConsiderationsHari Ananthan, Aditya Bansal, Kaushik Roy. 511-516 [doi]
• High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS ProcessVolkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman. 517-521 [doi]
• A High Performance Radiation-Hard Field Programmable Analog Array Ji Luo, Joseph B. Bernstein, J. Ari Tuchman, Hu Huang, Kuan-Jung Chung, Anthony L. Wilson. 522-527 [doi]
• The Design and Analysis of Non-Uniform Down-Sized Differential Distributed AmplifiersAhmad Yazdi, Payam Heydari. 528-533 [doi]
• An Asymmetric SRAM Cell to Lower Gate LeakageNavid Azizi, Farid N. Najm. 534-539 [doi]