Table of Contents

• Multi-Gate MOSFET DesignGerhard Knoblinger. 3 [doi]
• SUB-45nm Technology and Design ChallengesGerhard Knoblinger, James Tschanz, Marcal Pol. 3 [doi]
• Self-Adaptive Systems to Drive out the Nano-Scale DevilMarcal Pol. 4 [doi]
• SUB 45nm Low Power Design ChallengesJames Tschanz. 4 [doi]
• DFT and Test: Ensuring Product QualityNagesh Nagapalli. 5 [doi]
• Quality Driven Manufacturing and SOC DesignsSrikanth Venkataraman, Nagesh Nagapalli, Lech Józwiak. 5 [doi]
• DFM, DFY, Debug and Diagnosis: The Loop to Ensure YieldSrikanth Venkataraman. 5 [doi]
• Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCsLech Józwiak. 6 [doi]
• DFM-EDA s Salvation or its Excuse for Being out of Touch with Engineering?Resve Saleh, Pallab K. Chatterjee, Ivan Pesic, Robbert Dobkins, Mike Smayling, Joseph Sawicki. 7-8 [doi]
• Tipping Point for New Design Technologies: DFM, Low Power and ESLJeong-Taek Kong. 9-14 [doi]
• VariationDuane S. Boning, Karthik Balakrishnan, Hong Cai, Nigel Drego, Ali Farahanchi, Karen Gettings, Daihyun Lim, Ajay Somani, Hayden Taylor, Daniel Truque, Xiaolin Xie. 15-20 [doi]
• A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage VariationTakashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu. 21-26 [doi]
• Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOSRajani Kuchipudi, Hamid Mahmoodi. 27-32 [doi]
• Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM DesignsRouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif. 33-40 [doi]
• A New Simulation Method for NBTI Analysis in SPICE EnvironmentRakesh Vattikonda, Yansheng Luo, Alex Gyure, Xiaoning Qi, Sam C. Lo, Mahmoud Shahram, Yu Cao, Kishore Singhal, Dino Toffolon. 41-46 [doi]
• Combating NBTI Degradation via Gate SizingXiangning Yang, Kewal K. Saluja. 47-52 [doi]
• Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for ReliabilityBenoit Dubois, Jean-Baptiste Kammerer, Luc Hebrard, Francis Braun. 53-58 [doi]
• A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting DisplaysAram Shin, Sang-Jun Hwang, Seung Woo Yu, Man Young Sung. 59-66 [doi]
• Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive DriversMosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud. 67-72 [doi]
• Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced SkewSherif A. Tawfik, Volkan Kursun. 73-78 [doi]
• Speculative Energy Scheduling for LDPC DecodingWeihuang Wang, Gwan Choi. 79-84 [doi]
• Dynamic Power Management by Combination of Dual Static Supply VoltagesKanak Agarwal, Kevin J. Nowka. 85-92 [doi]
• Low Voltage Buffered Bandgap ReferencePeter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik. 93-97 [doi]
• A DLL Based Multiphase Hysteretic DC-DC ConverterPengfei Li, Rizwan Bashirullah. 98-101 [doi]
• Statistical Timing Analysis Considering Spatial CorrelationsHong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen. 102-107 [doi]
• Systematic Design of a Flash ADC for UWB ApplicationsLiang Rong, E. Martin I. Gustafsson, Ana Rusu, Mohammed Ismail. 108-114 [doi]
• EDA to the Rescue of the Silicon RoadmapThomas W. Williams. 115-118 [doi]
• Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect SolutionsArthur Nieuwoudt, Yehia Massoud. 119-126 [doi]
• FinFET Based SRAM Design for Low Standby Power ApplicationsTamer Cakici, Kee-Jong Kim, Kaushik Roy. 127-132 [doi]
• Compact Modeling of a PD SOI MESFET for Wide Temperature DesignsAsha Balijepalli, Joseph Ervin, Yu Cao, Trevor Thornton. 133-138 [doi]
• Modeling of PMOS NBTI Effect Considering Temperature VariationHong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. 139-144 [doi]
• Device Footprint Scaling for Ultra Thin Body Fully Depleted SOIJie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong. 145-152 [doi]
• A Low-Power Multi-Pin Maze Routing MethodologyAhmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry. 153-158 [doi]
• An Aggregation-Based Algebraic Multigrid Method for Power Grid AnalysisPei-Yu Huang, Huan-Yu Chou, Yu-Min Lee. 159-164 [doi]
• Design and Analysis of Tree+Local Meshes Clock ArchitectureGustavo R. Wilke, Rajeev Murgai. 165-170 [doi]
• An Efficient Algorithm for RLC Buffer InsertionZhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi. 171-175 [doi]
• Fast Crosstalk Repair by Quick Timing Change EstimationNahmsuk Oh, Alireza Kasnavi, Peivand F. Tehrani. 176-184 [doi]
• Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM ArraysMinh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson. 185-191 [doi]
• Cross Layer Error Exploitation for Aggressive Voltage ScalingAmin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Rouwaida Kanj. 192-197 [doi]
• A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking SystemsHwisung Jung, Massoud Pedram. 198-203 [doi]
• Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded SystemsYongpan Liu, Huazhong Yang, Robert P. Dick, Hui Wang, Li Shang. 204-209 [doi]
• A Unified Optimal Voltage Selection Methodology for Low-Power SystemsFoad Dabiri, Roozbeh Jafari, Ani Nahapetian, Majid Sarrafzadeh. 210-218 [doi]
• Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters InsertionCharbel J. Akl, Magdy A. Bayoumi. 219-224 [doi]
• A 8b 10Ms/s Low Power Pipelined A/D ConverterBi Yuan, Yi Zhang, Lili He. 225-228 [doi]
• First-Order Continuous-Time Sigma-Delta ModulatorYamei Li, Lili He. 229-232 [doi]
• Reducing EPL Alignment Errors for Large VLSI LayoutsYokesh Kumar, Prosenjit Gupta. 233-238 [doi]
• Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOSZhiyu Liu, Volkan Kursun. 239-244 [doi]
• Efficient Signal Integrity Verification of Multi-Coupled Transmission Lines with Asynchronously Switching Non-Linear DriversTaeyong Je, Yungseon Eo. 245-250 [doi]
• Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design GoalsLing Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng. 251-256 [doi]
• Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal VariationsBao Liu. 257-262 [doi]
• Tests on Symmetry and Continuity between BSIM4 and BSIM5Xudong Niu, Yan Song, Bo Li, Wei Bian, Yadong Tao, Feng Liu, Jinhua Hu, Yu Chen, Frank He. 263-268 [doi]
• Interface Specification Assurance MethodsNaiyong Jin, Taoyong Ni. 269-274 [doi]
• Multi-Dimensional Circuit and Micro-Architecture Level OptimizationZhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan. 275-280 [doi]
• A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET ArraysNigel Drego, Anantha Chandrakasan, Duane S. Boning. 281-286 [doi]
• Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated CircuitsRishi Bhooshan. 287-292 [doi]
• Processing High Volume Scan Test Results for Yield LearningAlfred L. Crouch, Phil Burlison, Dennis J. Ciplickas. 293-298 [doi]
• Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-ArchitectureWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu. 299-304 [doi]
• Comparative Robustness of CML Phase Detectors for Clock and Data Recovery CircuitsDavid Rennie, Manoj Sachdev. 305-310 [doi]
• Inductive Fault Analysis for Test and Diagnosis of DNA Sensor ArraysDaniela De Venuto, Bruno Riccò. 311-316 [doi]
• Fine-Grained Redundancy in AddersPatrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy. 317-321 [doi]
• MEMS Failure Probability Prediction and Quality Enhancement Using Neural NetworksAbby A. Ilumoka, Hong Lang Tan. 322-326 [doi]
• Variation Aware Timing Based Placement Using Fuzzy ProgrammingVenkataraman Mahalingam, N. Ranganathan. 327-332 [doi]
• Variation Analysis of CAM CellsAmol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. 333-338 [doi]
• Design-for-Manufacture for Multi Gate Oxide CMOS ProcessQi Lin, Mei Ma, Tony Vo, Jenny Fan, Xin Wu, Richard Li, Xiao Yu Li. 339-343 [doi]
• Intelligent Random Vector Generator Based on Probability Analysis of Circuit StructureYu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho. 344-349 [doi]
• Power Delivery Aware Floorplanning for Voltage Island DesignsYici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong. 350-355 [doi]
• Passive Modeling of Interconnects by Waveform ShapingBoyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy. 356-361 [doi]
• A Power Network Synthesis Method for Industrial Power Gating DesignsKaijian Shi, Zhian Lin, Yi-Min Jiang. 362-367 [doi]
• Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-ConstraintYuan Cai, Sudhakar M. Reddy, Bashir M. Al-Hashimi. 368-373 [doi]
• Challenges in Evaluations for a Typical-Case Design MethodologyYuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato. 374-379 [doi]
• SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAsHamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew. 380-385 [doi]
• Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip MultiprocessorsXiaofang Wang, Sotirios G. Ziavras. 386-391 [doi]
• A High Frequency PWM Controller in HV Bi-CMOS Process Considering SOI Self-HeatingGautam Kumar Singh, Santosh Kumar Panigrahi. 392-397 [doi]
• Sensitivity Based Link Insertion for Variation Tolerant Clock Network SynthesisJoon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan. 398-403 [doi]
• Built-In Test of RF Mixers Using RF Amplitude DetectorsChaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham. 404-409 [doi]
• Glitch Control with Dynamic Receiver Threshold AdjustmentMichael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas. 410-415 [doi]
• Programmable High Speed Multi-Level Simultaneous Bidirectional I/OYong Sin Kim, Sung-Mo Kang. 416-419 [doi]
• A Fault Tolerant Design Methodology for Threshold Logic Gates and Its OptimizationsManoj Kumar Goparaju, Spyros Tragoudas. 420-425 [doi]
• Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing OptimizationKumar Yelamarthi, Chien-In Henry Chen. 426-431 [doi]
• Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect CharacterizationMehboob Alam, Arthur Nieuwoudt, Yehia Massoud. 432-437 [doi]
• System Level Estimation of Interconnect Length in the Presence of IP BlocksTaraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh. 438-443 [doi]
• Energy-Minimization Model for Fill SynthesisRasit Onur Topaloglu. 444-451 [doi]
• On-Chip Inductance in X Architecture Enabled DesignSantosh Shah, Arani Sinha, Li Song, Narain D. Arora. 452-457 [doi]
• Impact of Variability on Clock Skew in H-tree Clock NetworksAshok Narasimhan, Ramalingam Sridhar. 458-466 [doi]
• A DOE Set for Normalization-Based Extraction of Fill Impact on CapacitancesAndrew B. Kahng, Rasit Onur Topaloglu. 467-474 [doi]
• SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory DesignJeong-Yeol Kim, Ho-Soon Shin, Jong-Bae Lee, Moon-Hyun Yoo, Jeong-Taek Kong. 475-480 [doi]
• Pareto-Front Computation and Automatic Sizing of CPPLLsJun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann. 481-486 [doi]
• InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error VisualizationKai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco. 487-494 [doi]
• Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series ModelJoonsung Park, Hongjoong Shin, Jacob A. Abraham. 495-500 [doi]
• Design of a Window Comparator with Adaptive Error Threshold for Online Testing ApplicationsAmit Laknaur, Rui Xiao, Sai Raghuram Durbha, Haibo Wang. 501-506 [doi]
• High-Frequency-Measurement-Based Frequency-Variant Transmission Line Characterization and Circuit Modeling for Accurate Signal Integrity VerificationHyunsik Kim, Yungseon Eo. 507-512 [doi]
• Achieving Low-Cost Linearity Test and Diagnosis of Sigma Delta ADCs via Frequency-Domain Nonlinear Analysis and MacromodelingGuo Yu, Peng Li, Wei Dong. 513-518 [doi]
• Fully Digital Optimized Testing and Calibration Technique for Sigma Delta ADC sDaniela De Venuto, Leonardo Reyneri. 519-526 [doi]
• Cell-Based Semicustom Design of Zigzag Power Gating CircuitsYoungsoo Shin, Hyung-Ock Kim. 527-532 [doi]
• Lookup Table-Based Adaptive Body Biasing of Multiple MacrosByunghee Choi, Youngsoo Shin. 533-538 [doi]
• A Simple Flip-Flop Circuit for Typical-Case Designs for DFMToshinori Sato, Yuji Kunitake. 539-544 [doi]
• A High Performance, Scalable Multiplexed Keeper TechniqueJaydeep P. Kulkarni, Kaushik Roy. 545-549 [doi]
• On-Line Adjustable Buffering for Runtime Power ReductionAndrew B. Kahng, Sherief Reda, Puneet Sharma. 550-555 [doi]
• Programmable Engines for Embedded Systems: The New ChallengesMarc Duranton. 556-557 [doi]
• Soft-Errors Phenomenon Impacts on Design for Reliability TechnologiesMarc Derbey. 558-559 [doi]
• Forging Tighter Connections Between Design and Manufacturing in the Nanometer AgeJoseph Sawicki. 560-566 [doi]
• 3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function MethodDongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu. 567-572 [doi]
• Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-DesignEunseok Song, Heeseok Lee, Jungtae Lee, Woojin Jin, Kiwon Choi, Sa-Yoon Kang. 573-579 [doi]
• Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration TechnologySyed M. Alam, Robert E. Jones, Shahid Rauf, Ritwik Chatterjee. 580-585 [doi]
• A Design Methodology for Matching Improvement in Bandgap ReferencesJuan Pablo Martinez Brito, Hamilton Klimach, Sergio Bampi. 586-594 [doi]
• Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA DesignsDavid Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee. 595-601 [doi]
• Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current AnalysisCheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang. 602-606 [doi]
• Transistor-Level Synthesis for Low-Power ApplicationsDimitri Kagaris, Themistoklis Haniotakis. 607-612 [doi]
• Assertion Checkers in Verification, Silicon Debug and In-Field DiagnosisMarc Boule, Jean-Samuel Chenard, Zeljko Zilic. 613-620 [doi]
• Self-Time Regenerators for High-Speed and Low-Power InterconnectJae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw. 621-626 [doi]
• Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky FactorizationHong Li, Jitesh Jain, Venkataramanan Balakrishnan, Cheng-Kok Koh. 627-632 [doi]
• General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic CircuitsNing Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu. 633-638 [doi]
• Investigating Crosstalk in Sub-Threshold CircuitsMini Nanua, David Blaauw. 639-646 [doi]
• A Model for Timing Errors in Processors with Parameter VariationSmruti R. Sarangi, Brian Greskamp, Josep Torrellas. 647-654 [doi]
• Parameter-Variation-Aware Analysis for Noise RobustnessMosin Mondal, Kartik Mohanram, Yehia Massoud. 655-659 [doi]
• Future Prediction of Self-Heating in Short Intra-Block WiresKenichi Shinkai, Masanori Hashimoto, Takao Onoye. 660-665 [doi]
• Thermal-Aware Placement for FPGAs Using Electrostatic Charge ModelJavid Jaffari, Mohab Anis. 666-671 [doi]
• Do Digital Design and Variability Mix like Oil and Water?Jacques Benkoski, Michelle Clancy, Shankar Krishnamoorthy, David Holt, Ravi Subramanian, Clive Bittlestone, Tsuyoshi Yamamoto, Andrew Kanhg. 672-676 [doi]
• An Exploratory Study on Statistical Timing Analysis and Parametric Yield OptimizationAyhan A. Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, Long-Ching Yeh. 677-684 [doi]
• From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit AnalysisAmith Singhee, Rob A. Rutenbar. 685-692 [doi]
• Defect or Variation? Characterizing Standard Cell Behavior at 90nm and belowRobert C. Aitken. 693-698 [doi]
• A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI TechnologyChoongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski. 699-702 [doi]
• Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column RedundancyUthman Alsaiari, Resve Saleh. 703-710 [doi]
• Small-Delay Defect Detection in the Presence of Process VariationsRajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham. 711-716 [doi]
• Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan ArchitectureRajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov. 717-722 [doi]
• On Accelerating Soft-Error Detection by Targeted Pattern GenerationAlodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu. 723-728 [doi]
• Enhanced Identification of Strong Robustly Testable PathsEdward Flanigan, Spyros Tragoudas. 729-736 [doi]
• Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension ReductionZhuo Feng, Guo Yu, Peng Li. 737-742 [doi]
• Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and CapacitanceNing Lu, Judy H. McCullen. 743-748 [doi]
• Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi DecodersYang Liu, Tong Zhang, Jiang Hu. 749-754 [doi]
• Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay CalibrationSivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia. 755-760 [doi]
• Designing and Validating Process-Variation-Aware Cell LibrariesAli Dasdan, Jinfeng Liu, Sridhar Tirumala, Kayhan Küçükçakar. 761-770 [doi]
• Transferring Optical Proximity Correction (OPC) Effect into Optical ModeJianliang Li, Qiliang Yan, Lawrence S. Melvin III. 771-775 [doi]
• OPC-Friendly De-Compaction with Timing Constraints for Standard Cell LayoutsTetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. 776-781 [doi]
• An Automated and Fast OPC Algorithm for OPC-Aware Layout DesignYe Chen, Zheng Shi, Xiaolang Yan. 782-787 [doi]
• A New Method of Implementing Hierarchical OPCYufu Zhang, Zheng Shi. 788-794 [doi]
• A New Flexible Algorithm for Random Yield ImprovementSubarna Sinha, Qing Su, Linni Wen, Frank Lee, Charles Chiang, Yi-Kan Cheng, Jin-Lien Lin, Yu-Chyi Harn. 795-800 [doi]
• Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process VariationsArthur Nieuwoudt, Tamer Ragheb, Hamid Nejati, Yehia Massoud. 801-806 [doi]
• Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration AlgorithmS. Ramsundar, Ahmad A. Al-Yamani, Dhiraj K. Pradhan. 807-813 [doi]
• Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization TechniquesShubhankar Basu, Priyanka Thakore, Ranga Vemuri. 814-820 [doi]
• Redundant Via Insertion in Restricted Topology LayoutsKevin W. McCullen. 821-828 [doi]
• Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical PlacementChen Li 0004, Cheng-Kok Koh. 829-834 [doi]
• Congestion Driven Buffer Planning for X-ArchitectureHongjie Bai, Sheqin Dong, Xianlong Hong. 835-840 [doi]
• Probabilistic Congestion Prediction with Partial BlockagesZhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi. 841-846 [doi]
• OPC-Friendly Bus Driven FloorplanningHua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong. 847-852 [doi]
• Power-Gating Aware FloorplanningHailin Jiang, Malgorzata Marek-Sadowska. 853-860 [doi]
• Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating DesignsFrederic Worm, Patrick Thiran, Paolo Ienne. 861-866 [doi]
• An Infrastructure IP for Online Testing of Network-on-Chip Based SoCsPraveen Bhojwani, Rabi N. Mahapatra. 867-872 [doi]
• Provisioning On-Chip Networks under Buffered RC Interconnect Delay VariationsMosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud. 873-878 [doi]
• Virtual Channels Planning for Networks-on-ChipTing-Chun Huang, Ümit Y. Ogras, Radu Marculescu. 879-884 [doi]
• A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated CircuitsVyas Krishnan, Srinivas Katkoori. 885-892 [doi]
• MARS-S: Modeling and Reduction of Soft Errors in Sequential CircuitsNatasa Miskov-Zivanov, Diana Marculescu. 893-898 [doi]
• An SEU-Tolerant Programmable Frequency DividerLiang Wang, Suge Yue, Yuanfu Zhao, Long Fan. 899-904 [doi]
• A TMR Scheme for SEU Mitigation in Scan Flip-FlopsRoystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty. 905-910 [doi]
• Variation Impact on SER of Combinational CircuitsKrishnan Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. 911-916 [doi]
• MEMESTAR: A Simulation Framework for Reliability Evaluation over Multiple EnvironmentsChristian J. Hescott, Drew C. Ness, David J. Lilja. 917-922 [doi]