Table of Contents

• Tutorial 1: The Promise of High-Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit ApplicationsK. Maitra. 3 [doi]
• Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm TechnologiesChris Kim. 4 [doi]
• Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration TechnologyRobert E. Jones. 5 [doi]
• Tutorial 4: Robust System Design in Scaled CMOSSubhasish Mitra. 6 [doi]
• Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve?Hillary Hunter. 7 [doi]
• Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM)Praveen Elakkumanan. 8-9 [doi]
• Plenary Speech 1P1: Shrinking time-to-market through global value chain integrationDrew Gude. 15 [doi]
• Plenary Speech 1P2: Bounding the Endless Verification LoopRobert Hum. 16-17 [doi]
• A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOSMark Lysinger, François Jacquet, Mehdi Zamanian, David McClure, Philippe Roche, Naren Sahoo, John Russell. 23-29 [doi]
• Error-Tolerant SRAM Design for Ultra-Low Power Standby OperationHuifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar. 30-34 [doi]
• Error Protected Data Bus Inversion Using Standard DRAM ComponentsMaurizio Skerlj, Paolo Ienne. 35-42 [doi]
• Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI InterconnectsChittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas. 43-46 [doi]
• Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including ReorderingTiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis. 47-52 [doi]
• Fast and Accurate Waveform Analysis with Current Source ModelsVineeth Veetil, Dennis Sylvester, David Blaauw. 53-56 [doi]
• An Efficient Method for Fast Delay and SI Calculation Using Current Source ModelsXin Wang, Alireza Kasnavi, Harold Levy. 57-61 [doi]
• Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay ModelYi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai. 62-67 [doi]
• Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting CodesAvijit Dutta, Abhijit Jas. 68-73 [doi]
• Output Remapping Technique for Soft-Error Rate Reduction in Critical PathsQian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang. 74-77 [doi]
• IR Drop Reduction via a Flip-Flop Resynthesis TechniqueJiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen. 78-83 [doi]
• Noise Interaction Between Power Distribution Grids and SubstrateDaniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson. 84-89 [doi]
• Luncheon Keynote SpeechAntun Domic. 90-91 [doi]
• Fundamental Data Retention Limits in SRAM Standby Experimental ResultsAnimesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran. 92-97 [doi]
• Quality of a Bit (QoB): A New Concept in Dependable SRAMHidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto. 98-102 [doi]
• Cache Design for Low Power and High YieldBaker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham. 103-107 [doi]
• Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance VariationsXin Li, Yu Cao. 108-113 [doi]
• High Output Resistance and Wide Swing Voltage Charge Pump CircuitTian Xia, Stephen Wyatt. 114-117 [doi]
• Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal BusesKrishnan Sundaresan, Nihar R. Mahapatra. 118-122 [doi]
• A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory DesignSaravanan Ramamoorthy, Haibo Wang, Sarma B. K. Vrudhula. 123-126 [doi]
• Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold OperationJoseph F. Ryan, Benton H. Calhoun. 127-132 [doi]
• Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFMTaro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai. 133-136 [doi]
• Accurate Temperature Estimation for Efficient Thermal ManagementShervin Sharifi, Chunchen Liu, Tajana Simunic Rosing. 137-142 [doi]
• Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS LogicKumar Yelamarthi, Chien-In Henry Chen. 143-147 [doi]
• Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy AnalysisSeyed-Abdollah Aftabjahani, Linda S. Milor. 148-151 [doi]
• A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current MirrorsLei Zhang, Zhiping Yu, Xiangqing He. 152-155 [doi]
• Robust Estimation of Timing Yield with Partial Statistical Information on Process VariationsLin Xie, Azadeh Davoodi. 156-161 [doi]
• Variation Aware Spline Center and Range Modeling for Analog Circuit PerformanceShubhankar Basu, Balaji Kommineni, Ranga Vemuri. 162-167 [doi]
• High-Quality Circuit Synthesis for Modern TechnologiesLech Józwiak, Artur Chojnacki, Aleksander Slusarczyk. 168-173 [doi]
• ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL SynthesisSaraju P. Mohanty. 174-177 [doi]
• Improving the Efficiency of Power Management Techniques by Using Bayesian ClassificationHwisung Jung, Massoud Pedram. 178-183 [doi]
• An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical SystemsJason D. Lee, Nikhil Gupta, Praveen Bhojwani, Rabi N. Mahapatra. 184-189 [doi]
• Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic BehaviorHyunok Oh. 190-193 [doi]
• Thermal-Aware IR Drop Analysis in Large Power GridYu Zhong, Martin D. F. Wong. 194-199 [doi]
• A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process VariationsAmit Goel, Sarma B. K. Vrudhula, Feroze Taraporevala, Praveen Ghanta. 200-206 [doi]
• Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge ModelShah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev. 207-212 [doi]
• Characterization of Standard Cells for Intra-Cell Mismatch VariationsSavithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda. 213-219 [doi]
• Full-Chip Leakage Verification for Manufacturing Considering Process VariationsTao Li, Zhiping Yu. 220-223 [doi]
• Processor Verification with hwBugHuntSangeetha Sudhakrishnan, Liying Su, Jose Renau. 224-229 [doi]
• Enhancing the Testability of RTL Designs Using Efficiently Synthesized AssertionsMohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi. 230-235 [doi]
• Efficient Selection of Observation Points for Functional TestsJian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram. 236-241 [doi]
• A Novel Test Generation Methodology for Adaptive DiagnosisRajsekhar Adapa, Edward Flanigan, Spyros Tragoudas. 242-245 [doi]
• Timing-Aware Multiple-Delay-Fault DiagnosisVishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. 246-253 [doi]
• A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCsDhruva Ghai, Saraju P. Mohanty, Elias Kougianos. 257-260 [doi]
• Dominant Substrate Noise Coupling Mechanism for Multiple Switching GatesEmre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin. 261-266 [doi]
• A Statistic-Based Approach to Testability AnalysisChuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen. 267-270 [doi]
• Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation ModesFeng Liu, Jin He, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang, Mansun Chan. 271-276 [doi]
• On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout ProblemTsu-Shuan Chang, Manish Kumar, Teng-Sheng Moh, Chung-Li Tseng. 277-282 [doi]
• Architecting for Physical Verification Performance and ScalingJohn Ferguson, Robert Todd. 283-288 [doi]
• Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement AlgorithmHaixia Yan, Qiang Zhou, Xianlong Hong. 289-292 [doi]
• CMOS Based Low Cost Temperature SensorNeehar Jandhyala, Lili He, Morris Jones. 293-296 [doi]
• An SSO Based Methodology for EM Emission Estimation from SoCsSukumar Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar. 297-300 [doi]
• Fast Timing Update under the Effect of IR DropMuzhou Shao. 301-304 [doi]
• Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter FluctuationsZhiyu Liu, Sherif A. Tawfik, Volkan Kursun. 305-310 [doi]
• Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process VariationsSherif A. Tawfik, Volkan Kursun. 311-316 [doi]
• A Low Energy Two-Step Successive Approximation Algorithm for ADC DesignRicky Yiu-kee Choi, Chi-Ying Tsui. 317-320 [doi]
• Automated Specific Instruction Customization Methodology for Multimedia Processor AccelerationKang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto. 321-324 [doi]
• Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design MethodologiesSrinivasa R. S. T. G, Jandhyala Srivatsava, Narahari Tondamuthuru R. 325-329 [doi]
• Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) DesignDhruva Ghai, Saraju P. Mohanty, Elias Kougianos. 330-333 [doi]
• Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy ValidationC. R. Venugopal, Prasanth Soraiyur, Jagannath Rao. 334-337 [doi]
• Hotspot Based Yield Prediction with Consideration of CorrelationsQing Su, Charles Chiang, Jamil Kawa. 338-343 [doi]
• A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM ApplicationsMaharaj Mukherjee, Kanad Chakraborty. 344-347 [doi]
• A Passive 915 MHz UHF RFID TagJosé Carlos S. Palma, César A. M. Marcon, Fabiano Hessel, Eduardo Bezerra, Guilherme Rohde, Luciano Azevedo, Carlos Eduardo Reif, Carolina Metzler. 348-351 [doi]
• Crosstalk Noise Variation Assessment and Analysis for the Worst Process CornerJae-Seok Yang, Andrew R. Neureuther. 352-356 [doi]
• DFM Based Detailed Routing Algorithm for ECP and CMPYin Shen, Yici Cai, Qiang Zhou, Xianlong Hong. 357-360 [doi]
• Instruction Scheduling for Variation-Originated Variable LatenciesToshinori Sato, Shingo Watanabe. 361-364 [doi]
• Hotspot Prevention Using CMP Model in Design Implementation FlowNorma Rodriguez, Li Song, Shishir Shroff, Kuang Han Chen, Taber Smith, Wilbur Luo. 365-368 [doi]
• The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale EraYoung-Gu Kim, Soo Hwan Kim, Hoon Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo. 369-372 [doi]
• Computation of Waveform Sensitivity Using Geometric Transforms for SSTARatnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava. 373-378 [doi]
• On Efficient and Robust Constraint Generation for Practical Layout LegalizationSambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy. 379-384 [doi]
• Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit FamilyCharbel J. Akl, Magdy A. Bayoumi. 385-390 [doi]
• Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device FailuresEric Karl, Dennis Sylvester, David Blaauw. 391-395 [doi]
• Characterizing the Impact of Substrate Noise on High-Speed Flash ADCsParastoo Nikaeen, Boris Murmann, Robert W. Dutton. 396-400 [doi]
• Analytical Noise-Rejection Model Based on Short Channel MOSFETVinay Jain, Payman Zarkesh-Ha. 401-406 [doi]
• A High-Performance Bus Architecture for Strongly Coupled InterconnectsMichael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas. 407-410 [doi]
• A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOSZahra Sadat Ebadi, Resve A. Saleh. 411-416 [doi]
• A Holistic Approach to SoC VerificationAlicia Strang, David Potts, Shankar Hemmady. 417-422 [doi]
• A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel’s Test ChipsNathaniel August. 423-428 [doi]
• Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium DevicesJae Wook Kim, Boris Murmann, Robert W. Dutton. 429-432 [doi]
• Verification of IP-Core Based SoC sAnil Deshpande. 433-436 [doi]
• Innovative Test Solutions for Pin-Limited MicrocontrollersMatthew G. Stout, Kenneth P. Tumin. 437-440 [doi]
• XStatic: A Simulation Based ESD Verification and Debug EnvironmentGanesh R. Shamnur, Rajesh R. Berigei. 441-444 [doi]
• Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor GroupingSachin Shrivastava, Harindranath Parameswaran. 445-449 [doi]
• Cell Swapping Based Migration Methodology for Analog and Custom LayoutsShabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy. 450-455 [doi]
• A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory ModelsPaul Pao-Fang Cheng. 456-459 [doi]
• System Verilog for Quality of Results (QoR)Ravi Surepeddi. 460-464 [doi]
• Power Delivery System: Sufficiency, Efficiency, and StabilityZhen Mu. 465-469 [doi]
• Thermal Aware Global Routing of VLSI Chips for Enhanced ReliabilityAseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir. 470-475 [doi]
• Clock Skew Analysis via Vector Fitting in Frequency DomainLing Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng. 476-479 [doi]
• An Approach for a Comprehensive QA Methodology for the PDKsSridhar Joshi, Ravi Perumal, Kamesh V. Gadepally, Mark Young. 480-483 [doi]
• Strategies for Quality CAD PDKsKamesh V. Gadepally, Mark Young, James Lin, Andy Franklin, Ravi Perumal, Sridhar Joshi. 484-487 [doi]
• Variability Analysis for sub-100nm PD/SOI Sense-AmplifierSaibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang. 488-491 [doi]
• Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation FrameworkManuel Sellier, Jean Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy. 492-497 [doi]
• Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable ElectronicsRasit Onur Topaloglu. 498-501 [doi]
• A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital DesignSaurabh Sinha, Asha Balijepalli, Yu Cao. 502-507 [doi]
• Adaptive Branch and Bound Using SAT to Estimate False CrosstalkMurthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler. 508-513 [doi]
• Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting RoutingPeng-Yang Hung, Ying-Shu Lou, Yih-Lang Li. 514-519 [doi]
• Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock DistributionShinya Abe, Masanori Hashimoto, Takao Onoye. 520-525 [doi]
• A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI DesignsSandeep Gupta, Jaya Singh, Abhijit Roy. 526-530 [doi]
• Study on the Si-Ge Nanowire MOSFETs with the Core-Shell StructureYue Fu, Jin He, Feng Liu, Jie Feng, Chenyue Ma, Lining Zhang. 531-536 [doi]
• Elastic Timing Scheme for Energy-Efficient and Robust PerformanceRupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu. 537-542 [doi]
• Statistical Models and Frequency-Dependent Corner Models for Passive DevicesNing Lu. 543-548 [doi]
• A Thermal-Friendly Load-Balancing Technique for Multi-Core ProcessorsEnric Musoll. 549-552 [doi]
• Analytical Model for the Propagation Delay of Through Silicon ViasDiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De. 553-556 [doi]
• Sampling Error Estimation in High-Speed Sampling Systems Introduced by the Presence of Phase Noise in the Sampling ClockSalam D. Marougi. 557-563 [doi]
• A QoS Scheduler for Real-Time Embedded SystemsDavid Matschulat, César A. M. Marcon, Fabiano Hessel. 564-567 [doi]
• FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement ReceiverJames Helton, Chien-In Henry Chen, David M. Lin, James B. Y. Tsui. 568-571 [doi]
• A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution NetworksJeff Mueller, Resve A. Saleh. 572-577 [doi]
• Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing TestSanjiv Taneja. 585 [doi]
• Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and QualityChandu Visweswariah. 586 [doi]
• Plenary Speech 2P3: The Greening of The SoC - How Electrical Engineers Will Save The WorldRich Goldman. 587-588 [doi]
• System-in-Package Technology: Opportunities and ChallengesAnna Fontanelli. 589-593 [doi]
• Printed Circuit Board Assembly Test Process and Design for TestabilityThao Nguyen, Navid Rezvani. 594-599 [doi]
• Fast Evaluation Method for Transient Hot Spots in VLSI ICs in PackagesJe-Hyoung Park, Ali Shakouri, Sung-Mo Kang. 600-603 [doi]
• An Implementation of Performance-Driven Block and I/O Placement for Chip-Package CodesignMing-Fang Lai, Hung-Ming Chen. 604-607 [doi]
• Techniques for Early Package Closure in System-in-PackagesSanthosh Coimbatore Vaidyanathan, Amit Mangesh Brahme, Sukumar Jairam. 608-613 [doi]
• Fast Shape Optimization of Metallization Patterns for DMOS Based DriverBo Yang, Shigetoshi Nakatake, Hiroshi Murata. 617-620 [doi]
• MAISE: An Interconnect Simulation Engine for Timing and Noise AnalysisFrank Liu, Peter Feldmann. 621-626 [doi]
• Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step RoundingXiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu. 627-632 [doi]
• Sequential Path Delay Fault Identification Using Encoded Delay Propagation SignaturesEdward Flanigan, Arkan Abdulrahman, Spyros Tragoudas. 633-636 [doi]
• 2D Decomposition Sequential Equivalence Checking of System Level and RTL DescriptionsDan Zhu, Tun Li, Yang Guo, Sikun Li. 637-642 [doi]
• Automated Standard Cell Library Analysis for Improved Defect ModelingJason G. Brown, R. D. (Shawn) Blanton. 643-648 [doi]
• A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed TestHo Fai Ko, Nicola Nicolici. 649-654 [doi]
• Finite-Point Gate Model for Fast Timing and Power AnalysisDinesh Ganesan, Alexander V. Mitev, Janet Meiling Wang, Yu Cao. 657-662 [doi]
• Noise-Aware On-Chip Power Grid Considerations Using a Statistical ApproachDaniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors. 663-669 [doi]
• Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O InterfacesHai Lan, Ralf Schmitt, Chuck Yuan. 670-675 [doi]
• Practical Clock Tree Robustness Signoff MetricsAnand Rajaram, Raguram Damodaran, Arjun Rajagopal. 676-679 [doi]
• Hierarchical Soft Error Estimation Tool (HSEET)Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, K. Unlu. 680-683 [doi]
• Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)Yiran Chen, XiaoBin Wang, Hai Li, Harry Liu, Dimitar V. Dimitrov. 684-690 [doi]
• Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube InterconnectArthur Nieuwoudt, Yehia Massoud. 691-696 [doi]
• Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale CrossbarRajat Subhra Chakraborty, Swarup Bhunia. 697-701 [doi]
• Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell YieldRouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif. 702-707 [doi]
• High Resolution Read-Out Circuit for DNA Label-Free Detection SystemDaniela De Venuto, Bruno Riccò. 708-711 [doi]
• Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter VariationLin Xie, Azadeh Davoodi. 712-717 [doi]
• Characterizing Intra-Die Spatial Correlation Using Spectral Density MethodQiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng. 718-723 [doi]
• Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and NoiseArthur Nieuwoudt, Jamil Kawa, Yehia Massoud. 724-729 [doi]
• Process-Variation Statistical Modeling for VLSI Timing AnalysisJui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, Charlie Chung-Ping Chen. 730-733 [doi]
• A Design Model for Random Process VariabilityVictoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic. 734-737 [doi]
• A Scratch-Pad Memory Aware Dynamic Loop Scheduling AlgorithmOzcan Ozturk, Mahmut T. Kandemir, Sri Hari Krishna Narayanan. 738-743 [doi]
• Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture PlatformAllen C. Cheng. 744-749 [doi]
• Runtime Validation of Transactional Memory SystemsKaiyu Chen, Sharad Malik, Priyadarsan Patra. 750-756 [doi]
• SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor SystemsMakoto Sugihara. 757-762 [doi]
• Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI EffectWenping Wang, Shengqi Yang, Yu Cao. 763-768 [doi]
• An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology NodeChin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu. 769-773 [doi]
• Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature VariationBin Zhang, Michael Orshansky. 774-779 [doi]
• Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded SystemsFoad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sarrafzadeh. 780-783 [doi]
• A Basis for Formal Robustness CheckingGörschwin Fey, Rolf Drechsler. 784-789 [doi]
• Quantified Impacts of Guardband Reduction on Design Process OutcomesKwangok Jeong, Andrew B. Kahng, Kambiz Samadi. 790-797 [doi]
• Partitioning for Selective Flip-Flop Redundancy in Sequential CircuitsUthman Alsaiari, Resve A. Saleh. 798-803 [doi]
• A Root-Finding Method for Assessing SRAM StabilityRouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif. 804-809 [doi]
• Cellwise OPC Based on Reduced Standard Cell LibraryHailong Jiao, Lan Chen. 810-814 [doi]
• On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring CircuitsAmlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown. 815-820 [doi]
• Interval Based X-Masking for Scan Compression ArchitecturesAnshuman Chandra, Rohit Kapur. 821-826 [doi]
• Two New Methods for Accurate Test Set Relaxation via Test Set ReplacementStelios Neophytou, Maria K. Michael. 827-831 [doi]
• Embedded Deterministic Test Exploiting Care Bit Clustering and Seed BorrowingAdam B. Kinsman, Nicola Nicolici. 832-837 [doi]
• A Built-in Test and Characterization Method for Circuit Marginality Related FailuresAlodeep Sanyal, Sandip Kundu. 838-843 [doi]
• On Chip Jitter Measurement through a High Accuracy TDCAkhil Garg, Prashant Dubey. 844-847 [doi]
• Robust Analog Design for Automotive Applications by Design Centering with Safe Operating AreasUdo Sobe, Karl-Heinz Rooch, Andreas Ripp, Michael Pronath. 848-854 [doi]
• Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust OperationSherif A. Tawfik, Volkan Kursun. 855-860 [doi]
• Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal InterconnectYu Zhou, Somnath Paul, Swarup Bhunia. 861-866 [doi]
• Statistic Analysis of Power/Ground Networks Using Single-Node SOR MethodZuying Luo, Sheldon X.-D. Tan. 867-872 [doi]
• IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power OptimizationXiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong. 873-876 [doi]