Table of Contents

• Ultra-low latency NoC testing via pseudo-random test pattern compactionHervé Tatenguem, Alessandro Strano, Vineeth Govind, Jaan Raik, Davide Bertozzi. 1-6 [doi]
• 2 multi-standard turbo decoderRachid Al-Khayat, Amer Baghdadi, Michel Jézéquel. 1-7 [doi]
• Improving logic-to-memory ratio in an embedded Multi-Processor system via code compressionRoberto Airoldi, Piia Saastamoinen, Jari Nurmi. 1-4 [doi]
• Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCsLeandro Möller, Leandro Soares Indrusiak, Luciano Ost, Fernando Gehm Moraes, Manfred Glesner. 1-4 [doi]
• Instrumentation-driven model detection for dataflow graphsIlya Chukhman, William Plishker, Shuvra S. Bhattacharyya. 1-8 [doi]
• Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCsLiang Guang, Ethiopia Nigussie, Juha Plosila, Jouni Isoaho, Hannu Tenhunen. 1-7 [doi]
• Resource-shared custom instruction generation under performance/area constraintsDi Wu, Junwhan Ahn, Imyong Lee, Kiyoung Choi. 1-6 [doi]
• System-level software performance simulation considering out-of-order processor executionRoman Plyaskin, Thomas Wild, Andreas Herkersdorf. 1-7 [doi]
• Application-aware spinlock control using a hardware scheduler in MPSoC platformsDiandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout. 1-6 [doi]
• Scalability analysis of release and sequential consistency models in NoC based multicore systemsAbdul Naeem, Axel Jantsch, Zhonghai Lu. 1-7 [doi]
• Asynchronous parallel MPSoC simulation on the Single-Chip Cloud ComputerChristoph Roth, Simon Reder, Gokhan Erdogan, Oliver Sander, Gabriel Marchesan Almeida, Harald Bucher, Jürgen Becker. 1-8 [doi]
• PowerMemo: A power profiling tool for mobile devices in an emulated wireless environmentShiao Li Tsao, Chih-Chen Kao, Ilter Suat, Yuchen Kuo, Yi-Hsin Chang, Cheng-Kun Yu. 1-5 [doi]
• Effects of scaling a coarse-grain reconfigurable array on power and energy consumptionWaqar Hussain, Tapani Ahonen, Jari Nurmi. 1-5 [doi]
• Statistical timing characterizationZeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme. 1-4 [doi]
• An automated framework for the simulation of mapping solutions on heterogeneous MPSoCsAntonio Miele, Christian Pilato, Donatella Sciuto. 1-6 [doi]
• Hierarchical control flow matching for source-level simulation of embedded softwareKun Lu, Daniel Müller-Gritschneder, Ulf Schlichtmann. 1-5 [doi]
• Dataflow-based reconfigurable architecture for streaming applicationsAnja Niedermeier, Jan Kuper, Gerard J. M. Smit. 1-4 [doi]
• Thermal/performance trade-off in network-on-chip architecturesDavide Zoni, Simone Corbetta, William Fornaciari. 1-8 [doi]
• Tiny application-specific programmable processor for BCH decodingAnthony Van Herrewege, Ingrid Verbauwhede. 1-4 [doi]
• Efficient VLSI architectures of QPP interleavers for LTE turbo decodersMartin Broich, Tobias G. Noll. 1-6 [doi]
• A double data rate 8T-cell SRAM architecture for systems-on-chipSaleh Abdel-Hafeez, Mohammad Shatnawi, Ann Gordon-Ross. 1-4 [doi]
• A hybrid chip interconnection architecture with a global wireless network overlaid on top of a wired network-on-chipLing Wang, Zhen Wang, Yingtao Jiang. 1-4 [doi]
• A flexible platform architecture for Gbps wireless communicationJeroen Declerck, Prabhat Avasare, Miguel Glassee, Amir Amin, Erik Umans, Andy Dewilde, Praveen Raghavan, Martin Palkovic. 1-6 [doi]
• Enhancing Cache Coherent Architectures with access patterns for embedded manycore systemsJussara Marandola, Stéphane Louise, Loïc Cudennec, Jean-Thomas Acquaviva, David A. Bader. 1-7 [doi]
• A multi-banked shared-l1 cache architecture for tightly coupled processor clustersMohammad Reza Kakoee, Vladimir Petrovic, Luca Benini. 1-5 [doi]
• CRAVE: An advanced constrained random verification environment for SystemCFinn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler. 1-7 [doi]