Abstract is missing.
- Implementation and evaluation of configuration scrubbing on CGRAs: A case studySyed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen. 1-8 [doi]
- Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systemsChe-Chuan Kuo, Kun-Chih Chen, En-Jui Chang, An-Yeu Wu. 1-4 [doi]
- Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platformsMarco Balboni, Francisco Triviño, Jose Flich, Davide Bertozzi. 1-6 [doi]
- Split-cost communication model for improved MPSoC application mappingMaximilian Odendahl, Jerónimo Castrillon, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid. 1-8 [doi]
- Crosstalk avoidance coding for reliable data transmission of network on chipsZahra Shirmohammadi, Seyed Ghassem Miremadi. 1-4 [doi]
- Efficient on-chip vector processing for multicore processorsSpiridon F. Beldianu, Sotirios G. Ziavras. 1-4 [doi]
- A cycle accurate simulation framework for asynchronous NoC designFederico Terraneo, Davide Zoni, William Fornaciari. 1-8 [doi]
- A family of modular area- and energy-efficient QRD-accelerator architecturesUpasna Vishnoi, Tobias G. Noll. 1-8 [doi]
- Achieving QoS in NoC-based MPSoCs through Dynamic Frequency ScalingGuilherme Guindani, Fernando Gehm Moraes. 1-6 [doi]
- Efficient distributed memory management in a multi-core H.264 decoder on FPGAJiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch. 1-4 [doi]
- On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCsBenedikt Noethen, Oliver Arnold, Gerhard Fettweis. 1-7 [doi]
- Dependency analysis and visualization tool for Kactus2 IP-XACT design frameworkJoni-Matti Määttä, Mikko Honkonen, Tommi Korhonen, Erno Salminen, Timo D. Hämäläinen. 1-6 [doi]
- Comparison of analog transactions using statisticsAlexander W. Rath, Volkan Esen, Wolfgang Ecker. 1-6 [doi]
- Study of adaptive detection for MIMO-OFDM systemsEssi Suikkanen, Janne Janhunen, Shahriar Shahabuddin, Markku J. Juntti. 1-4 [doi]
- Framework for industrial embedded system product development and managementArttu Leppakoski, Erno Salminen, Timo D. Hämäläinen. 1-6 [doi]
- ViSA: A highly efficient slot architecture enabling multi-objective ASIP coresPeter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker. 1-8 [doi]
- System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systemsLorenzo Zuolo, Gabriele Miorandi, Cristian Zambelli, Piero Olivo, Davide Bertozzi. 1-6 [doi]
- Prefetching across a shared memory tree within a Network-on-Chip architectureJamie Garside, Neil C. Audsley. 1-4 [doi]
- FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compilerFlorian Stock, Andreas Koch 0001, Dietmar Hildenbrand. 1-6 [doi]
- Scheduling of parallelized synchronous dataflow actorsZheng Zhou, Karol Desnos, Maxime Pelcat, Jean-François Nezan, William Plishker, Shuvra S. Bhattacharyya. 1-10 [doi]
- Adaptive QoS techniques for NoC-based MPSoCsMarcelo Ruaro, Everton Alceu Carara, Fernando Gehm Moraes. 1-6 [doi]
- SW and HW speculative Nelder-Mead execution for high performance unconstrained optimizationArtur Mariano, Paulo Garcia, Tiago Gomes. 1-5 [doi]
- Partitioning constraints and signal routing approach for multi-FPGA prototyping platformMariem Turki, Habib Mehrez, Zied Marrakchi, Mohamed Abid. 1-4 [doi]
- TNODE: A low power sensor node processor for secure wireless networksGoran Panic, Oliver Schrape, Thomas Basmer, Frank Vater, Klaus Tittelbach-Helmrich. 1-4 [doi]
- Evaluating the scalability of test busesAlexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Cristiano Lazzari, Marcelo Soares Lubaszewski. 1-6 [doi]
- A novel SAD architecture for variable block size motion estimation in HEVC video codingPurnachand Nalluri, Luis Nero Alves, Antonio Navarro. 1-4 [doi]
- Extending IP-XACT to embedded system HW/SW integrationAntti Kamppi, Lauri Matilainen, Joni-Matti Määttä, Erno Salminen, Timo D. Hämäläinen. 1-8 [doi]