Abstract is missing.
- System-Level Synthesis of Application Specific Systems using A* Search and Generalized Force-Directed HeuristicsChunho Lee, Miodrag Potkonjak, Wayne Wolf. 2-7 [doi]
- Toward a Practical Methodology for Completely Characterizing the Optimal Design SpaceStephen A. Blythe, Robert A. Walker. 8-13 [doi]
- Grammar-Based Hardware Synthesis of Data Communication ProtocolsJohnny Öberg, Anshul Kumar, Ahmed Hemani. 14-19 [doi]
- ADOPT: Efficient Hardware Address Generation in Distributed Memory ArchitecturesMiguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man. 20-25 [doi]
- Breakpoints and Breakpoint Detection in Source Level EmulationGernot Koch, Udo Kebschull, Wolfgang Rosenstiel. 26 [doi]
- Layout-Driven RTL Binding Techniques for High-Level SynthesisMin Xu, Fadi J. Kurdahi. 33-38 [doi]
- Eliminating False Loops Caused by Sharing in Control PathAlan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee. 39-44 [doi]
- An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL DescriptionsMichael Münch, Manfred Glesner, Norbert Wehn. 45-50 [doi]
- A Constructive Method for Exploiting Code MotionLuiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess. 51-56 [doi]
- Synthesis of Low-Power Selectively-Clocked Systems from High-Level SpecificationLuca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli. 57 [doi]
- Bus-Based Communication Synthesis on System-LevelMichael Gasteier, Manfred Glesner. 65-70 [doi]
- Hardware/Software Partitioning with Iterative Improvement HeuristicsPetru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli. 71-76 [doi]
- The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded SystemsAlessandro Balboni, William Fornaciari, M. Vincenzi, Donatella Sciuto. 77-82 [doi]
- A Codesign Experiment in Acoustic Echo Cancellation: GMDFaLaurent Freund, Michel Israël, Frédéric Rousseau, J. M. Bergé, Michel Auguin, Cécile Belleudy, Guy Gogniat. 83 [doi]
- Memory Organization for Improved Data Cache Performance in Embedded ProcessorsPreeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau. 90-95 [doi]
- Size-Constrained Code Placement for Cache Miss Rate ReductionHiroyuki Tomiyama, Hiroto Yasuura. 96-104 [doi]
- Instruction Set Design and Optimizations for Address Computation in DSP ArchitecturesGuido Araujo, Ashok Sudarsanam, Sharad Malik. 102-107 [doi]
- Modeling Multicomputer Task Allocation as a Vector Packing ProblemJames E. Beck, Daniel P. Siewiorek. 115-120 [doi]
- A Comparison of Functional and Structural PartitioningFrank Vahid, Thuy Dm Le, Yu-Chin Hsu. 121-126 [doi]
- Flow Graph Balancing for Minimizing the Required Memory BandwidthSven Wuytack, Francky Catthoor, Gjalt G. de Jong, Bill Lin, Hugo De Man. 127-132 [doi]
- Throughput Optimization in Disk-Based Real-Time Application Specific SystemsStephen Docy, Inki Hong, Miodrag Potkonjak. 133-138 [doi]
- Testability Insertion in Behavioral DescriptionsFrank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel. 139-144 [doi]