Table of Contents

• Overview of the Scalable Communications CoreJeffrey D. Hoffman, David Arditti Ilitzky, Anthony Chun, Aliaksei Chapyzhenka. 3-8 [doi]
• Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture DesignYoussef Atat, Nacer-Eddine Zergainoh. 9-14 [doi]
• A Flexible Datapath Interconnect for Embedded ApplicationsMagnus Själander, Per Larsson-Edefors, Magnus Björk. 15-20 [doi]
• HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded SystemsNicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert. 21-28 [doi]
• Technological hybridization for efficient runtime reconfigurable FPGAsNicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon. 29-34 [doi]
• Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemCAlisson V. De Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher. 35-40 [doi]
• Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAsMichael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele. 41-46 [doi]
• Transparent Dataflow Execution for Embedded ApplicationsMateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro. 47-54 [doi]
• A Novel Methodology for Temperature-Aware Placement and Routing of FPGAsKostas Siozios, Dimitrios Soudris. 55-60 [doi]
• A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable ArchitecturesRicardo Ferreira, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso. 61-66 [doi]
• 3D-Vias Aware Quadratic Placement for 3D VLSI CircuitsRenato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis. 67-72 [doi]
• Minimum-Congestion Placement for Y-interconnects: Some studies and observationsTuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta. 73-80 [doi]
• Design of a MCML Gate Library Applying Multiobjective OptimizationRoberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfgang H. Krautschneider. 81-85 [doi]
• Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variationsLucas Brusamarello, Roberto da Silva, Ricardo A. L. Reis, Gilson I. Wirth. 86-91 [doi]
• A Hash-based Approach for Functional Regularity Extraction During Logic SynthesisAngelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto. 92-97 [doi]
• Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T ApplicationsChin-Long Wey, Wei-Chien Tang, Shin-Yo Lin. 98-106 [doi]
• A 10T Non-Precharge Two-Port SRAM for 74 Power Reduction in Video ProcessingHiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto. 107-112 [doi]
• Design and Analysis of Low Power Dynamic Bus Based on RLC simulationShanq-Jang Ruan, Shang-Fang Tsai, Yu-Ting Pai. 113-118 [doi]
• Interconnect Power Optimization Based on Timing AnalysisLiu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong. 119-124 [doi]
• Overdrive Power-Gating Techniques for Total Power MinimizationMindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson. 125-132 [doi]
• Phase-Noise Driven System Design of Fractional-N Frequency Synthesizers and Validation With Measured ResultsHimanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick Wolf. 133-138 [doi]
• Systematic Design Optimization Methodology for Multi-Band CMOS Low Noise AmplifiersArthur Nieuwoudt, Tamer Ragheb, Yehia Massoud. 139-144 [doi]
• An Automated Passive Analog Circuit Synthesis Framework using Genetic AlgorithmsAngan Das, Ranga Vemuri. 145-152 [doi]
• Data Recovery Block Design for Impulse Modulated Power Line Communications in a MicroprocessorRajesh Thirugnanam, Dong Sam Ha, T. M. Mak. 153-158 [doi]
• Coverage Driven Verification applied to Embedded SoftwareDjones Lettnin, Markus Winterholer, Axel G. Braun, Joachim Gerlach, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel. 159-164 [doi]
• Improving the Quality of Bounded Model Checking by Means of Coverage EstimationUlrich Kühne, Daniel Große, Rolf Drechsler. 165-170 [doi]
• Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase PrognosisPrashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani. 171-178 [doi]
• A New Test Data Compression Scheme for Multi-scan DesignsTeng Lin, Jianhua Feng, Yangyuan Wang. 179-185 [doi]
• On the Compressibility of Power Grid ModelsJoão M. S. Silva, L. Miguel Silveira. 186-191 [doi]
• Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and MitigationTiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell. 192-197 [doi]
• Code-coverage Based Test Vector Generation for SystemC DesignsAlair Dias Jr., Diógenes Cecilio da Silva Jr.. 198-206 [doi]
• Enhancing the Tolerance to Power-Supply Instability in Digital CircuitsJorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 207-212 [doi]
• Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP BlocksTaraneh Taghavi, Majid Sarrafzadeh. 213-218 [doi]
• An Efficient Analytical Approach to Path-Based Buffer InsertionHamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi. 219-224 [doi]
• Integrated Gate and Wire Sizing at Post Layout LevelNarender Hanchate, Nagarajan Ranganathan. 225-232 [doi]
• Generating Realistic Stimuli for Accurate Power Grid AnalysisPedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira. 233-238 [doi]
• CMP-aware Maze Routing Algorithm for Yield EnhancementHailong Yao, Yici Cai, Xianlong Hong. 239-244 [doi]
• Statistical Gate Sizing for Yield Enhancement at Post Layout LevelNarender Hanchate, Nagarajan Ranganathan. 245-252 [doi]
• Automatic Retargeting of Binary Utilities for Embedded Code GenerationAlexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado. 253-258 [doi]
• A Programmable Stream Processing Engine for Packet Manipulation in Network ProcessorsMichael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf. 259-264 [doi]
• A System-level Performance Evaluation Methodology for Netwrok Processors Based on Network Calculus Analytical ModelingFrederico De Faria, Marius Strum, Wang Jiang Chau. 265-272 [doi]
• High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD CircuitSaihua Lin, Huazhong Yang, Rong Luo. 273-278 [doi]
• Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and FloorplanZhiPeng Liu, Jinian Bian, Qiang Zhou, Hui Dai. 279-284 [doi]
• Design of a Novel CNTFET-based Reconfigurable Logic GateJ. Liu, Ian O Connor, David Navarro, Frédéric Gaffiot. 285-290 [doi]
• Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICsShubhankar Basu, Ranga Vemuri. 291-298 [doi]
• Inserting Data Encoding Techniques into NoC-Based SystemsJosé Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis. 299-304 [doi]
• Performance Evaluation for Three-Dimensional Networks-On-ChipBrett Feero, Partha Pratim Pande. 305-310 [doi]
• Application - specific NoC platform design based on System Level OptimizationLazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris. 311-316 [doi]
• Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction CodingAmlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Cristian Grecu. 317-324 [doi]
• Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO DecodingDi Wu, Johan Eilert, Dake Liu, Dandan Wang, Naofal Al-Dhahir, Hlaing Minn. 325-330 [doi]
• A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCsAntonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. 331-336 [doi]
• Partial Product Reduction for Parallel CubingJames E. Stine, Jeff M. Blank. 337-342 [doi]
• Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r FormatSreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas. 343-350 [doi]
• A Methodology and Toolset to Enable SystemC and VHDL Co-simulationRichard Maciel, Bruno Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo. 351-356 [doi]
• Designing Memory Subsystems Resilient to Process VariationsMahmoud Ben Naser, Yao Guo, Csaba Andras Moritz. 357-363 [doi]
• Asymmetrically Banked Value-Aware Register FilesShuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras. 363-368 [doi]
• A MEMS Ultra-Stable Short Duration Current Pulse GeneratorAndrew Tam, Sazzadur Chowdhury. 369-374 [doi]
• Investigating Simple Low Latency Reliable Multiported Register FilesAndrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin. 375-382 [doi]
• Activity-Aware Registers Placement for Low Power Gated Clock Tree ConstructionWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu. 383-388 [doi]
• A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive DesignsPrashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay. 389-394 [doi]
• On the Limitations of Power Macromodeling TechniquesFelipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos. 395-400 [doi]
• Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding SchemeK. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas. 401-408 [doi]
• Performance of Graceful Degradation for Cache FaultsHyunjin Lee, Sangyeun Cho, Bruce R. Childers. 409-415 [doi]
• A Quantum Algorithm for Finding Minimum Exclusive-Or ExpressionsMarinos Sampson, Dimitrios Voudouris, George K. Papakonstantinou. 416-421 [doi]
• Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri NetsMehrdad Najibi, Mahtab Niknahad, Hossein Pedram. 422-427 [doi]
• On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and ImprovementMehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi. 428-436 [doi]
• FPGA Prototyping of a Two-Phase Self-Oscillating MicropipelineAbdel Ejnioui. 437-438 [doi]
• A Novel Reconfigurable Computation Unit for DSP ApplicationsJer Min Jou, Yun-Lung Lee, Chen-Yen Lin, Chien-Ming Sun. 439-444 [doi]
• Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC DecoderBruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi. 445-446 [doi]
• Vector Processing Support for FPGA-Oriented High Performance ApplicationsHongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie Hu. 447-448 [doi]
• An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsbAntonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. 449-450 [doi]
• MOTIM - A Scalable Architecture for Ethernet SwitchesErico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes. 451-452 [doi]
• Toward Memory-efficient Design of Video Encoders for Multimedia ApplicationsAvishek Saha, Santosh Ghosh, Shamik Sural, Jayanta Mukherjee. 453-454 [doi]
• MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable SystemsArun Janarthanan, Vijay Swaminathan, Karen A. Tomko. 455-456 [doi]
• Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable SystemS. Corbetta, Fabrizio Ferrandi, Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto. 457-458 [doi]
• Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic WorkloadEwerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes. 459-460 [doi]
• High Level RTOS Scheduler Modeling for a Fast Design ValidationFabiano Hessel, César A. M. Marcon, Tatiana Gadelha Serra dos Santos. 461-466 [doi]
• A High Swing Low Power CMOS Differential Voltage-Controlled Ring OscillatorLuciano Severino de Paula, Eric E. Fabris, Sergio Bampi, Altamiro Amadeu Susin. 467-470 [doi]
• A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level SimulationMahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram. 471-472 [doi]
• Power andPerformance Analysis for Early Design Space ExplorationCharles Thangaraj, Tom Chen. 473-478 [doi]
• Reliable Binary Signed Digit Number Adder DesignF. Kharbash, G. M. Chaudhry. 479-484 [doi]
• Voltage Pump Based on Self Clocked CellsHector Kirschenbaum, Alejandro De la Plaza. 485-487 [doi]
• Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution NetworksMohammad Azim Karami, Ali Afzali-Kusha, Reza Faraji-Dana, Masoud Rostami. 488-489 [doi]
• Subthreshold Pass Transistor Logic for Ultra-Low Power OperationVahid Moalemi, Ali Afzali-Kusha. 490-491 [doi]
• Design of A Double-Precision Floating- Point Multiply-Add-Fused Unit with Consideration of Data DependenceZhaolin Li, Gongqiong Li. 492-497 [doi]
• A comparison of low power architectures for digital delay measurementFranco Martin-Pirchio, Alfonso Chacon-Rodriguez, Pedro Julián, Pablo Sergio Mandolesi. 498-499 [doi]
• Efficient implementation of conduction modes for modelling skin effectSalvador Ortiz, Roberto Suaya. 500-505 [doi]
• A Low-Power High-Speed 4-Bit ADC for DS-UWB CommunicationsM. Khalilzadeh, A. Nabavi. 506-507 [doi]
• DSPstone Benchmark of CoDeL s Automated Clock Gating PlatformNainesh Agarwal, Nikitas J. Dimopoulos. 508-509 [doi]
• An External Memory Circuit Validation Algorithm for Large VLSI LayoutsYokesh Kumar, Prosenjit Gupta. 510-511 [doi]
• Modeling Subthreshold Leakage Current in General Transistor NetworksPaulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas. 512-513 [doi]
• Subthreshold 1-Bit Full Adder Cells in sub-100 nm TechnologiesVahid Moalemi, Ali Afzali-Kusha. 514-515 [doi]
• Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA ArchitecturesSoumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud. 516-517 [doi]