Abstract is missing.
- Message from the general and program chairsFernanda Lima Kastensmidt, Ricardo Reis, Leandro Soares Indrusiak, Gilles Sassatelli. [doi]
- NAND Flash memory: The driving technology in digital storage - Overview and challengesManuel d'Abreu. 1 [doi]
- Do we need wide flits in Networks-on-Chip?JungHee Lee, Chrysostomos Nicopoulos, Sung Joo Park, Madhavan Swaminathan, Jongman Kim. 2-7 [doi]
- Determining the test sources/sinks for NoC TAMsAlexandre M. Amory, Edson I. Moreno, Fernando Moraes, Marcelo Lubaszewski. 8-13 [doi]
- Real-time low-power task mapping in Networks-on-ChipM. Norazizi Sham Mohd Sayuti, Leandro Soares Indrusiak. 14-19 [doi]
- Using guiding heuristics to improve the dynamic checking of temporal properties in data dominated high-level designsAlair Dias Junior, Diogenes C. da Silva Junior. 20-25 [doi]
- Data extraction from SystemC designs using debug symbols and the SystemC APIJannis Stoppe, Robert Wille, Rolf Drechsler. 26-31 [doi]
- Embedded systems design for smart system integrationManfred Glesner, François Philipp. 32-33 [doi]
- LImbiC: An adaptable architecture description language model for developing an application-specific image processorCarsten Tradowsky, Tanja Harbaum, Shaver Deyerle, Jürgen Becker. 34-39 [doi]
- A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP contextVianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner. 40-45 [doi]
- A study on polymorphing superscalar processor dynamically to improve power efficiencySudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu. 46-51 [doi]
- Ground gated 8T SRAM cells with enhanced read and hold data stabilityHailong Jiao, Volkan Kursun. 52-57 [doi]
- A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributionsWorawit Somha, Hiroyuki Yamauchi, Ma YuYu. 58-63 [doi]
- Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage marginsKhawar Sarfraz, Volkan Kursun. 64-69 [doi]
- Dynamic encryption key design and management for memory data encryption in embedded systemsMei Hong, Hui Guo, Sri Parameswaran. 70-75 [doi]
- A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AESAnkita Arora, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran. 76-83 [doi]
- Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivitiesGuilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis. 84-89 [doi]
- STAIRoute: Global routing using monotone staircase channelsBapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal. 90-95 [doi]
- A novel tool flow for increased routing configuration similarity in multi-mode circuitsBrahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt. 96-101 [doi]
- Murphy goes 3DErik Jan Marinissen. 102 [doi]
- On-chip clock error characterization for clock distribution systemChuan Shan, Dimitri Galayko, François Anceau. 102-108 [doi]
- Using electromagnetic emanations for variability characterization in Flash-based FPGAsJimmy Tarrillo, Jorge Tonfat, Fernanda Lima Kastensmidt, Ricardo Reis, Florent Bruguier, Morgan Bourree, Pascal Benoit, Lionel Torres. 109-114 [doi]
- Whitespace-aware TSV arrangement in 3D clock tree synthesisXin Li, Wulong Liu, Haixiao Du, Yu Wang 0002, Yuchun Ma, Huazhong Yang. 115-120 [doi]
- A novel method to mitigate TSV electromigration for 3D ICsYuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vevet, Marc Belleville. 121-126 [doi]
- Program phase duration prediction and its application to fine-grain power managementSudarshan Srinivasan, Raghavan Kumar, Sandip Kundu. 127-132 [doi]
- Exploiting body biasing for leakage reduction: A case studyAndrea Manuzzato, Fabio Campi, Davide Rossi, Valentino Liberali, Davide Pandini. 133-138 [doi]
- Saliency-driven dynamic configuration of HMAX for energy-efficient multi-object recognitionSungho Park, Ahmed Al-Maashri, Yang Xiao, Kevin M. Irick, Vijaykrishnan Narayanan. 139-144 [doi]
- HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applicationsLech Józwiak. 145-146 [doi]
- Symbolic verification of timed asynchronous hardware protocolsKrishnaji Desai, Kenneth S. Stevens, John O'Leary. 147-152 [doi]
- Distributed resource management in NoC-based MPSoCs with dynamic cluster sizesGuilherme M. Castilhos, Marcelo Mandelli, Guilherme A. Madalozzo, Fernando Moraes. 153-158 [doi]
- On analyzing and mitigating SRAM BER due to random thermal noiseVikram B. Suresh, Sandip Kundu. 159-164 [doi]
- Routing-aware resource allocation for mixture preparation in digital microfluidic biochipsSudip Roy, Partha Pratim Chakrabarti, Srijan Kumar, Bhargab B. Bhattacharya, Krishnendu Chakrabarty. 165-170 [doi]
- On runtime task graph extraction in MPSoCKunal P. Ganeshpure, Sandip Kundu. 171-176 [doi]
- High and low side high voltage switch with over voltage and over current protectionWalter Luis Tercariol, Richard L. T. Saez, Ivan Carlos Ribeiro do Nascimento. 177-181 [doi]
- A novel optimization method for reversible logic circuit minimizationMatthew Morrison, Nagarajan Ranganathan. 182-187 [doi]
- Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoCLucas Tambara, Fernanda Lima Kastensmidt, Paolo Rech, Tiago R. Balen, Marcelo Lubaszewski. 188-193 [doi]
- Behavioral model of integrated qubit gates for quantum reversible logic designMatthew Lewandowski, Nagarajan Ranganathan, Matthew Morrison. 194-199 [doi]
- Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous coresNagarajan Venkateswaran, Kartik Lakshminarasimhan, Akash Sridhar, Prashanth Thinakaran, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Aswin Sridharan. 200-205 [doi]
- Comparison between three RTL implementations of the multiplicative inverse calculation of galois field elements based on a standard cells libraryOtacilio de Araujo Ramos Neto, Antonio Carlos Cavalcanti, Ruy Alberto Pisani Altafim. 206-211 [doi]
- Breaking power delivery walls using voltage stackingMircea Stan. 212 [doi]
- Memory subsystem architecture design for multimedia applicationsAlexsandro Cristovão Bonatto, Altamiro Amadeu Susin. 213-214 [doi]
- Design & implementation of software defined radios on a homogeneous multi-processor architectureRoberto Airoldi, Jari Nurmi. 215-216 [doi]
- Design of standard-cell libraries for asynchronous circuits with the ASCEnD flowMatheus Trevisan Moreira, Ney Laert Vilar Calazans. 217-218 [doi]
- Fault recovery communication protocol for NoC-based MPSoCsEduardo Weber Wächter, Alexandre M. Amory, Fernando Gehm Moraes. 219-220 [doi]
- A yield-driven regular layout synthesisCristina Meinhardt, Ricardo Reis. 221-222 [doi]
- Recent advances and challenges in physical design automationMarcelo O. Johann. 223 [doi]
- Branch-and-bound style resource constrained scheduling using efficient structure-aware pruningMingsong Chen, Saijie Huang, Geguang Pu, Prabhat Mishra. 224-229 [doi]
- Logic synthesis for manufacturability considering regularity and lithography printabilityLucas Machado, Vinícius Dal Bem, Francesc Moll, Sergio Gómez, Renato P. Ribas, André Inácio Reis. 230-235 [doi]
- Iterative remapping respecting timing constraintsLucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis. 236-241 [doi]