Table of Contents

• Introduction [doi]
• Open HW, Open Design SW, and the VC Ecosystem DilemmaJuan Antonio Carballo. 3-6 [doi]
• Enabling Technology for Analog Integration, invitedPaul Kempf. 9 [doi]
• System-on-Chip Design beyond 50 GHz, invitedS. P. Voinigescu, M. Gordon, C. Lee, T. Yao, A. Mangan, K. Yau. 10-13 [doi]
• Strained Si and the Future Direction of CMOS, invitedScott E. Thompson. 14-16 [doi]
• HW/SW Co-Design for SoC on Mobile Platforms, invitedJohan van der Tang, Harm van Rumpt, Dieter Kasperkovitz. 19-23 [doi]
• A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of AbstractionAlena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois. 24-29 [doi]
• A Software/Hardware Platform for Rapid Prototyping of Video and Multimedia DesignsPaul R. Schumacher, Marco Mattavelli, Adrian Chirila-Rus, Robert D. Turney. 30-33 [doi]
• The Software/Hardware Co-Debug Environment with EmulatorBaodong Yu, Xuecheng Zou. 34-38 [doi]
• DfM for SoC, invitedArtur Balasinski. 41-46 [doi]
• ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invitedYoon Huh, Peter Bendix, Kyungjin Min, Jau-Wen Chen, Ravindra Narayan, Larry D. Johnson, Steven H. Voldman. 47-53 [doi]
• System on Chip: Challenges and Design for Manufacturing, invitedAzzouz Nezar, Michael Creighton. 54-59 [doi]
• Leakage Current Variability in Nanometer Technologies, invitedMohab Anis, Mohamed H. Abu-Rahma. 60-63 [doi]
• Generic Modeling of Non-planar Dielectrics for 2 1/2D Parasitic ExtractionNur Kurt-Karsilayan. 64-69 [doi]
• Flash Memories for SoC: An Overview on System Constraints and Technology Issues, invitedLuca Larcher, Paolo Pavan, A. Maurelli. 73-77 [doi]
• Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and CircuitsDong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang. 78-81 [doi]
• PLL-Based Fractional-N Frequency SynthesizersFarhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski. 85-91 [doi]
• A New Topology for Power Control of High Efficiency Class-E Switched Mode Power AmplifierM. M. Tabriz, Nasser Masoumi. 92-95 [doi]
• A CMOS Quality Factor Enhanced Parallel Resonant LC-Tank with Independent Q and Frequency Tuning for RF Integrated FiltersJoshua K. Nakaska, James W. Haslett. 96-100 [doi]
• A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 SignalingHyoungsoo Kim, Youngsik Hur, Moonkyun Maeng, Franklin Bien, Soumya Chandramouli, Edward Gebara, Joy Laskar. 101-106 [doi]
• A Very Low-Power Flash A/D Converter Based on Cmos Inverter CircuitShih-Chang Hsia, Wen-Ching Lee. 107-110 [doi]
• Bidirectional Current-Mode Capacitor Multiplier in DC-DC Converter CompensationChia-Jung Chang, Ke-Horng Chen. 111-116 [doi]
• Design of 12-bit 100-MHz Current-Steering DAC for SoC ApplicationsChun-Yueh Huang, Tsung-Tien Hou, Chi-Chieh Chuang, Hung-Yu Wang. 117-122 [doi]
• A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC ArchitectureSyed Masood Ali, Rabin Raut, Mohamad Sawan. 123-126 [doi]
• A Comprehensive Model for On-Chip Spiral InductorsB. Khadem Hosseinieh, N. Masoumi. 127-131 [doi]
• Design and Optimization of Low-Voltage Low-Power Quasi-Floating Gate Digital CircuitsKenneth A. Townsend, James W. Haslett, Krzysztof Iniewski. 132-136 [doi]
• Life-Inspired Systems: Assuring Quality in the Era of Complexity, invitedLech Józwiak. 139-142 [doi]
• Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invitedJames B. Kuo. 143-148 [doi]
• A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial BackplaneCharles E. Berndt, Tad A. Kwasniewski. 149-153 [doi]
• Sigma-Delta Noise Shaping for Digital-to-Frequency and Digital-to-RF-Amplitude ConversionRobert B. Staszewski, Sameh Rezeq, Chih-Ming Hung, Patrick Cruise, John L. Wallberg. 154-159 [doi]
• Improved Wideband Low Distortion Cascaded Delta-Sigma ModulatorXiaolong Yuan, Andreas Gothenberg, Xiaobo Wu. 160-164 [doi]
• Noise Analysis of a CMOS Active Pixel Sensor for Tomographic MammographyMohammad Hadi Izadi, Karim S. Karim. 167-171 [doi]
• Conversion Time Analysis of Time Domain Digital Pixel Sensor in Uniform and Non-Uniform Quantizers, invitedAmine Bermak. 172-175 [doi]
• A Temperature, Supply Voltage Compensated Floating-Gate MOS Dosimeter Using V_TH ExtractorYanjie Wang, Yanbin Wang, Garry Tarr, Kris Iniewski. 176-179 [doi]
• A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS TechnologyHaigang Yang, Hongguang Sun, Jinghong Han, Jinbao Wei, Zengjin Lin, Shanhong Xia, Hua Zhong. 180-183 [doi]
• A Very Low Power CMOS Potentiostat for Bioimplantable ApplicationsMohammad M. Ahmadi, Graham A. Jullien. 184-189 [doi]
• An Acoustic Echo Canceller ChipMostafa Borhani, Vafa Sedghi. 193-198 [doi]
• A High-Performance Error Concealment Processor for Video DecoderShih-Chang Hsia, Shih Wen Chou. 199-202 [doi]
• A Scalable Low Power Imager Architecture for Compound-Eye Vision SensorsFarid Boussaïd, Chen Shoushun, Amine Bermak. 203-206 [doi]
• UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVCChoudhury A. Rahman, Wael M. Badawy. 207-210 [doi]
• A Hardware-Accelerated Framework with IP-Blocks for Application in MPEG-4Ihab Amer, Choudhury A. Rahman, Tamer Mohamed, Mohammed Sayed, Wael M. Badawy. 211-214 [doi]
• Digital RF Processing Techniques for SoC Radios, invitedRobert B. Staszewski, Khurram Muhammad, Dirk Leipold. 217-222 [doi]
• Low Power Bluetooth for Headset Applications, invitedChristian Cojocaru. 223-226 [doi]
• Design of 802.11 Access Point Chipsets for Enterprise Applications, invitedN. Patrick Kelly, Ben W. Jones, Nestor A. Fesas, John M. Morton. 227-232 [doi]
• VHDL Simulation and Modeling of an All-Digital RF TransmitterRobert B. Staszewski, Roman Staszewski, Poras T. Balsara. 233-238 [doi]
• Efficient Pattern-Based Emulation for IEEE 802.11a BasebandIl-Gu Lee, Heejung Yu, Sok-Kyu Lee, Jin Lee, Sin-Chong Park. 239-242 [doi]
• A 2.3GHz CMOS Transimpedance Preamplifier for Optical CommunicationYanjie Wang, Kris Iniewski. 243-246 [doi]
• A 0.65V, 1.9mW CMOS Low-Noise Amplifier at 5GHzYanjie Wang, M. Zamin Khan, Kris Iniewski. 247-251 [doi]
• Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on ChipDaniel Wiklund, Dake Liu. 252-256 [doi]
• A Tier 3 Software Defined AM RadioJung Ko, Vincent C. Gaudet, Robert Hang. 257-261 [doi]
• A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling CapacitanceS. A. Moghaddam, N. Masoumi, Caro Lucas. 265-269 [doi]
• A Structure Based Clustering Algorithm with Applications to VLSI Physical DesignJianhua Li, Laleh Behjat, Blair Schiffner. 270-274 [doi]
• Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite OptimizationP. L. Takouda, Miguel F. Anjos, Anthony Vannelli. 275-280 [doi]
• Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing AlgorithmNasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, J. Ghasemi. 283-288 [doi]
• Component-Based Methodology for Hardware Design of a Dataflow Processing NetworkRobert Grou-Szabo, Hany Ghattas, Yvon Savaria, Gabriela Nicolescu. 289-294 [doi]
• An Automatic Layout Generator for I/O CellsLi-Chun Tien, Jing-Jou Tang, Mi-Chang Chang. 295-300 [doi]
• Additional Knowledge of Bus Invert Coding SchemesTina Lindkvist. 301-303 [doi]
• High Level Extraction of SoC Architectural Information from Generic C Algorithmic DescriptionsMarco Mattavelli, Massimo Ravasi. 304-307 [doi]
• Practical Techniques for Performance Estimation of ProcessorsAbhijit Ray, Thambipillai Srikanthan, Wu Jigang. 308-311 [doi]
• A Multivalue Eigenvalue Based Circuit Partitioning TechniqueBlair Schiffner, Jianhua Li, Laleh Behjat. 312-316 [doi]
• A Hybrid Distributed Test Generation Method Using Deterministic and Genetic AlgorithmsHaidar Harmanani, Bassem Karablieh. 317-322 [doi]
• Accelerating Functional Simulation for Processor Based Designs, invitedRussell Klein, Tomasz Piekarz. 323-328 [doi]
• Instruction Based Testbench Architecture, invitedHo-Seok Choi, Seungbeom Lee, Sin-Chong Park. 329-333 [doi]
• A Precise Model for Leakage Power Estimation in VLSI CircuitsJ. Derakhshandeh, Nasser Masoumi, B. Kasiri, Y. Farazmand, Akbarzadeh, S. Aghnoot. 337-340 [doi]
• Turbo Codes - Digital IC DesignMoeed Israr, Tad A. Kwasniewski. 341-346 [doi]
• A Low Area and Low Power Programmable Baseband Processor ArchitectureEric Tell, Anders Nilsson, Dake Liu. 347-351 [doi]
• Power Saving of a Dynamic Width Controller for a Monolithic Current-Mode CMOS DC-DC ConverterHung-Ch Lee, Kuo-Tai Chang, Ke-Horng Chen, Wen Tsao Chen. 352-357 [doi]
• An Optimal ILP Model for Delay Time to Minimize Peak Power and AreaKi-Bog Kim, Chi-Ho Lin. 358-362 [doi]
• Power Reduction Technique Using Multi-vt LibrariesMeeta Srivastav, S. S. S. P. Rao, Himanshu Bhatnagar. 363-367 [doi]
• A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut NetsPayam Ghafari, Ehsan Mirhadi, Mohab Anis, Shawki Areibi, Mohamed I. Elmasry. 368-371 [doi]
• Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and CircuitsDong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su. 372-375 [doi]
• An Area-Efficient High-Speed AES S-Box MethodRichard Hobson, Scott Wakelin. 376-379 [doi]
• Low Latency and Power Efficient VD Using Register Exchanged State-Mapping AlgorithmSang-Ho Seo, Sin-Chong Park. 380-384 [doi]
• A Novel Design of a 6-GHz 8 X 8-b Pipelined MultiplierAmir Khatibzadeh, Kaamran Raahemifar. 387-391 [doi]
• Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS ProcessKwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen. 392-395 [doi]
• An Area-Reduced Scheme for Modulo 2n-1 Addition/SubtractionShaoqiang Bi, Warren J. Gross, Wei Wang 0003, Asim J. Al-Khalili, M. N. S. Swamy. 396-399 [doi]
• Very High Radix Scalable Montgomery MultipliersKyle Kelley, David Harris. 400-404 [doi]
• A Fast Full Search Equivalent Encoding Algorithm for Image Vector Quantization Based on the WHT and a LUTChul-hyung Ryu, Sung-Woong Ra. 405-409 [doi]
• Low-Power Programmable Signal Processing, invitedPaul E. Hasler. 413-418 [doi]
• An FPGA Based Accelerator for SAT Based Combinational Equivalence CheckingMona Safar, M. Watheq El-Kharashi, Ashraf Salem. 419-424 [doi]
• A Field-Programmable Analog Array Using Translinear ElementsDavid N. Abramson, Jordan D. Gray, Shyam Subramanian, Paul E. Hasler. 425-428 [doi]
• Hardware Acceleration of Deadlock Avoidance and Detection in Real-Time Operating SystemsP. Samson, P. Sinha. 429-433 [doi]
• System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog ArrayJoachim Becker, Fabian Henrici, Yiannos Manoli. 434-438 [doi]
• FPGA Implementation of Digital Controller for DC-DC Buck ConverterMiro Milanovic, Mitja Truntic, Primoz Slibar. 439-443 [doi]
• Systolic Array-Based String Matching Unit for Spam BlockingA. N. M. Ehtesham Rafiq, M. Watheq El-Kharashi, Fayez Gebali. 444-449 [doi]
• Performance Improvement of Configurable Processor Architectures Using a Variable Clock PeriodBill Pontikakis, François R. Boyer, Yvon Savaria. 454-458 [doi]
• Programmable Low Dropout Voltage RegulatorPaul E. Hasler, AiChen Low. 459-462 [doi]
• Three Dimensional System on Chip Technology, invitedEarl E. Swartzlander Jr.. 465-470 [doi]
• Simulation and Analysis of Network on Chip Architecture for Wireless Communication SystemSung-Rok Yoon, Sin-Chong Park. 471-475 [doi]
• Recent Advances and Future Trends in Low Power Wireless Systems for Medical ApplicationsKenneth A. Townsend, James W. Haslett, Tommy Kwong-Kin Tsang, Mourad N. El-Gamal, Krzysztof Iniewski. 476-481 [doi]
• Floating-Gate Devices, Circuits, and Systems, invitedPaul E. Hasler. 482-487 [doi]
• 10 GBPS over Copper Lines - State of the Art in VLSI, invitedStephen Bates, Kris Iniewski. 491-494 [doi]
• A Review of Current Standards Activities for High Speed Physical Layers, invitedThomas Palkert. 495-499 [doi]
• Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data CommunicationsMiao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang. 500-502 [doi]
• A High Efficiency 3GHz 24-dBm CMOS Linear Power Amplifier for RF ApplicationS. M. Rezaul Hasan. 503-507 [doi]
• A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking ApplicationsChing-Te Chiu, Chun-Chieh Chang, Shih-Min Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, Kai-Ming Feng. 508-513 [doi]
• High-Speed Serial Links: Design Trends and Challenges, invitedVladimir Stojanovic. 514 [doi]
• Synchronous Pipelined Relay Stations with Back-Pressure ToleranceRoger Su, Raman Mittal, Vivek Garg. 517-520 [doi]
• Modular Architecture for System-on-Chip Design of Scalable MEMS Optical Switch Actuator ControllerXiqun Zhu, Yuan Ma. 521-524 [doi]
• Architecture for Multi-processor SoC Platform Using Dedicated ChannelsGyongsu Lee, Sin-Chong Park. 525-529 [doi]
• Implementation of an On-Chip Bus Bridge between Heterogeneous Buses with Different Clock FrequenciesSangik Choi, Shinwook Kang. 530-534 [doi]
• Traffic Configuration for Evaluating Networks on ChipsZhonghai Lu, Axel Jantsch. 535-540 [doi]
• Orthogonalized Communication Architecture for MP-SoC with Global BusJin Lee, Sin-Chong Park. 541-545 [doi]
• MP SoCs Including Optical Interconnect. Technological Progresses and Challenges for CAD Tools DesignLuiza Gheorghe, Gabriela Nicolescu. 546-551 [doi]
• Transaction Analysis of Multiprocessor Based Platform with Bus MatrixSeungbeom Lee, Sin-Chong Park. 552-556 [doi]
• A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCsHung Tien Bui, Yvon Savaria. 557-562 [doi]