Table of Contents

• Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devicesSandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino, Leticia Maria Veiras Bolzani Poehls. 1-6 [doi]
• Predicting die-level process variations from wafer test data for analog devices: A feasibility studyS. Devarakond, J. McCoy, Amit Nahar, John M. Carulli Jr., S. Bhattacharya, A. Chatterjee. 1-6 [doi]
• Formal equivalence checking between high-level and RTL hardware designsCarlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau. 1-6 [doi]
• ISA configurability of an FPGA test-processor used for board-level interconnection testingJorge H. Meza Escobar, Jörg Sachße, Steffen Ostendorff, Heinz-Dietrich Wuttke. 1-6 [doi]
• A test time theorem and its applicationsPraveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal. 1-5 [doi]
• Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAsArwa Ben Dhia, Lirida A. B. Naviner, Philippe Matherat. 1-6 [doi]
• Markov chains hierarchical dependability models: Worst-case computationsMartin Kohlík, Hana Kubatova. 1-6 [doi]
• PrOCov: Probabilistic output coverage modelJoel Ivan Munoz Quispe, Marius Strum, Wang Jiang Chau. 1-6 [doi]
• Assessment of diagnostic test for automated bug localizationValentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar. 1-6 [doi]
• A RTN variation tolerant guard band design for a deeper nanometer scaled SRAM screening test: Based on EM Gaussians mixtures approximations model of long-tail distributionsWorawit Somha, Hiroyuki Yamauchi. 1-6 [doi]
• Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness studyPierre-Emmanuel Gaillardon, Hassan Ghasemzadeh, Giovanni De Micheli. 1-6 [doi]
• Local data fusion algorithm for fire detection through mobile robotGuilherme Freire Roberto, Kalinka Castelo Branco, José M. Machado, Alex R. Pinto. 1-6 [doi]
• Improving error detection with selective redundancy in software-based techniquesEduardo Chielle, José Rodrigo Azambuja, Raul S. Barth, Fernanda Lima Kastensmidt. 1-6 [doi]
• Fast fault injection techniques using FPGAsLuis Entrena. 1 [doi]
• Towards an automatic generation of diagnostic in-field SBST for processor componentsMario Schölzel, Tobias Koal, Stephanie Roder, Heinrich Theodor Vierhaus. 1-6 [doi]
• Parametric model calibration and measurement extraction for LFN using virtual instrumentationL. Francisco, Manuel Jimenez. 1-6 [doi]
• PASSAT 2.0: A multi-functional SAT-based testing frameworkRolf Drechsler, Melanie Diepenbeck, Stephan Eggersglüß, Robert Wille. 1 [doi]
• On the functional test of the BTB logic in pipelined and superscalar processorsD. Changdao, M. Graziano, E. Sanchez, Matteo Sonza Reorda, Maurizio Zamboni, N. Zhifan. 1-6 [doi]
• Pre-characterization procedure for a mixed mode simulation of IR-drop induced delaysM. Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, J. Jiang, Ilia Polian, Bernd Becker. 1-6 [doi]
• Analyzing and quantifying fault tolerance propertiesSybille Hellebrand. 1 [doi]
• Diagnostic modeling of digital systems with low- and high-level decision diagramsRaimund Ubar. 1 [doi]
• Low-cost DC BIST for analog circuits: A case studyPablo A. Petrashin, Carlos Dualibe, Walter J. Lancioni, Luis E. Toledo. 1-4 [doi]
• Diagnose of radiation induced single event effects in a PLL using a heavy ion microbeamSantiago Sondon, Alfredo Falcon, Pablo Sergio Mandolesi, Pedro Julián, Nahuel Vega, Francisco Nesprias, Jorge Davidson, Felix Palumbo, Mario Debray. 1-5 [doi]
• Embedded tutorial: Regaining hardware security and trustOzgur Sinanoglu. 1 [doi]
• Neutron sensitivity of integer and floating point operations executed in GPUsPaolo Rech, Caroline Aguiar, Christopher Frost, Luigi Carro. 1-6 [doi]
• Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applicationsWesley Silva, Eduardo Bezerra, Markus Winterholer, Djones Lettnin. 1-6 [doi]
• Bridge defect detection in nanometer CMOS circuits using Low VDD and body biasHector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastiàn A. Bota, Jaime Martinez, Jaume Segura. 1-6 [doi]
• SPICE level analysis of Single Event Effects in an OxRRAM cellK. Castellani-Coulié, Marc Bocquet, Hassen Aziza, Jean Michel Portal, Wenceslas Rahajandraibe, Christophe Muller. 1-5 [doi]
• Effect of aging on power integrity of digital integrated circuitsAlexandre Boyer, S. Ben Dhia. 1-5 [doi]
• Low cost signal reconstruction based testing of RF components using incoherent undersamplingDebesh Bhatta, Aritra Banerjee, Sabyasachi Deyati, Nicholas Tzou, Abhijit Chatterjee. 1-5 [doi]
• Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMsF. Lavratti, Leticia Maria Veiras Bolzani, Andrea Calimera, Fabian Vargas, Enrico Macii. 1-6 [doi]
• Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiverWenceslas Rahajandraibe, Haddad Fayrouz, Hassen Aziza, K. Castellani-Coulié, Jean Michel Portal. 1-4 [doi]
• Memristor-based filtering applicationsAlon Ascoli, Ronald Tetzlaff, Fernando Corinto, Miroslav Mirchev, Marco Gilli. 1-6 [doi]