Abstract is missing.
- Embedded systems in the wild: ZebraNet software, hardware, and deployment experiencesMargaret Martonosi. 1 [doi]
- Feedback linking: optimizing object code layout for updatesCarl von Platen, Johan Eker. 2-11 [doi]
- Minimizing downtime in seamless migrations of mobile applicationsKun Zhang, Santosh Pande. 12-21 [doi]
- Storing a persistent transactional object heap on flash memoryMichal Spivak, Sivan Toledo. 22-33 [doi]
- Deriving abstract transfer functions for analyzing embedded softwareJohn Regehr, Usit Duongsaa. 34-43 [doi]
- Pluggable abstract domains for analyzing embedded softwareNathan Cooprider, John Regehr. 44-53 [doi]
- Field-sensitive value analysis of embedded C programs with union types and pointer arithmeticsAntoine Miné. 54-63 [doi]
- Reducing the cost of conditional transfers of control by using comparison specificationsWilliam C. Kreahling, Stephen Hines, David B. Whalley, Gary S. Tyson. 64-71 [doi]
- Effective thread management on network processors with compiler analysisXiaotong Zhuang, Santosh Pande. 72-82 [doi]
- In search of near-optimal optimization phase orderingsPrasad Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson. 83-92 [doi]
- An EDF schedulability test for periodic tasks on reconfigurable hardware devicesKlaus Danne, Marco Platzner. 93-102 [doi]
- Faster WCET flow analysis by program slicingChrister Sandberg, Andreas Ermedahl, Jan Gustafsson, Björn Lisper. 103-112 [doi]
- Synthesizing safe state machines from EsterelSteffen Prochnow, Claus Traulsen, Reinhard von Hanxleden. 113-124 [doi]
- Efficient code generation from SHIM modelsStephen A. Edwards, Olivier Tardieu. 125-134 [doi]
- Generating optimized code from SCR specificationsTom Rothamel, Yanhong A. Liu, Constance L. Heitmeyer, Elizabeth I. Leonard. 135-144 [doi]
- Effective compiler generation by architecture descriptionStefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner. 145-152 [doi]
- Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processorJian-Jia Chen, Tei-Wei Kuo. 153-162 [doi]
- Compiler-directed thermal management for VLIW functional unitsMadhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 163-172 [doi]
- Bypass aware instruction scheduling for register file power reductionSanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie. 173-181 [doi]
- Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architecturesLeipo Yan, Thambipillai Srikanthan, Niu Gang. 182-188 [doi]
- BOTS: a constraint-based component system for synthesizing scalable software systemsRaju Pandey, Jeffrey Wu. 189-198 [doi]
- Optimizing compiler for shared-memory multiple SIMD architectureWeihua Zhang, Xinglong Qian, Ye Wang, Binyu Zang, Chuanqi Zhu. 199-208 [doi]