Table of Contents

• AFFORDe: Automatic Allocation and Floorplanning for SPMD ArchitectureWissem Chouchene, Rabie Ben Atitallah, Jean-Luc Dekeyser. 1-7 [doi]
• Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled EnvironmentRyotaro Sakai, Naru Sugimoto, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano. 8-14 [doi]
• Improvement of Line Coding Overhead Targeting Both Run-Length and DC-BalanceSarat Yoowattana, Tomohiro Yoneda. 15-22 [doi]
• Data and Commands Communication Protocol for Neuromorphic Platform ConfigurationAlessandro Siino, Francesco Barchi, Sergio Davies, Gianvito Urgese, Andrea Acquaviva. 23-30 [doi]
• Adaptive VC Organization and Arbitration for Efficient NoC DesignMasoud Oveis Gharan, Gul N. Khan. 31-38 [doi]
• Heuristic Based Routing Algorithm for Network on ChipAsma Benmessaoud Gabis, Marc Sevaux, Pierre Bomel, Mouloud Koudil, Karima Benatchba. 39-45 [doi]
• A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx PlatformYe Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro. 46-52 [doi]
• The Role of Self-Awareness and Hierarchical Agents in Resource Management for Many-Core SystemsMaximilian Gotzinger, Amir M. Rahmani, Martin Pongratz, Pasi Liljeberg, Axel Jantsch, Hannu Tenhunen. 53-60 [doi]
• Exploiting Large Memory Using 32-Bit Energy-Efficient Manycore ArchitecturesMohamed Lamine Karaoui, Pierre-Yves Peneau, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner. 61-68 [doi]
• 2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection Systems on MulticoresLau Phi Tuong, Keiji Kimura. 69-76 [doi]
• A Robust Methodology for Performance Analysis on Hybrid Embedded Multicore ArchitecturesRomain Saussard, Boubker Bouzid, Marius Vasiliu, Roger Reynaud. 77-84 [doi]
• A Data Locality and Memory Contention Analysis Method in Embedded NUMA Multi-core SystemsLin Li, Markus Fussenegger, Gordon Cichon. 85-92 [doi]
• Going beyond Mean and Median Programs PerformancesJulien Worms, Sid Ahmed Ali Touati. 93-100 [doi]
• High-Precision Performance Estimation of Dynamic Dataflow ProgramsMalgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli. 101-108 [doi]
• Power Management Controller for Online Power Saving in Network-on-ChipsStephanie Friederich, Marco Neber, Jürgen Becker. 109-116 [doi]
• Time-Triggered and Rate-Constrained On-chip Communication in Mixed-Criticality SystemsHamidreza Ahmadian, Roman Obermaisser, Mohammed Abuteir. 117-124 [doi]
• A Benes Based NoC Switching Architecture for Mixed Criticality Embedded SystemsSteve Kerrison, David May, Kerstin Eder. 125-132 [doi]
• NoC Based Virtualized Accelerators for Cloud ComputingHiliwi Leake Kidane, El-Bay Bourennane, Gilberto Ochoa-Ruiz. 133-137 [doi]
• cReComp: Automated Design Tool for ROS-Compliant FPGA ComponentKazushi Yamashina, Hitomi Kimura, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota. 138-145 [doi]
• Network on Chip and Parallel Computing in Embedded SystemsDihia Belkacemi, Youcef Bouchebaba, Mehammed Daoui, Mustapha Lalam. 146-152 [doi]
• Dynamic Ring-Based Multicast with Wavelength Reuse for Optical Network on ChipsFeiyang Liu, Haibo Zhang 0001, Yawen Chen, Zhiyi Huang 0001, Huaxi Gu. 153-160 [doi]
• Impact of on-chip power distribution on Temperature-Induced Faults in Optical NoCsMelika Tinati, Somayyeh Koohi, Shaahin Hessabi. 161-168 [doi]
• A Task Allocation Method for the DTTR Scheme Based on the Parallelism of TasksHiroshi Saito, Masashi Imai, Tomohiro Yoneda. 169-176 [doi]
• Accelerating Multicore Architecture Simulation Using Application ProfileKeiji Kimura, Gakuho Taguchi, Hironori Kasahara. 177-184 [doi]
• Performance Prediction of Application Mapping in Manycore Systems with Artificial Neural NetworksAbdoulaye Gamatié, Roman Ursu, Manuel Selva, Gilles Sassatelli. 185-192 [doi]
• High-Precision Power Modelling of the Tegra K1 Variable SMP Processor ArchitectureKristoffer Robin Stokke, Håkon Kvale Stensland, Pål Halvorsen, Carsten Griwodz. 193-200 [doi]
• Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy ExplorationAnastasiia Butko, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli, David Novo, Lionel Torres, Michel Robert. 201-208 [doi]
• Communication-Based Power Modelling for Heterogeneous Multiprocessor ArchitecturesBaptiste Roux, Matthieu Gautier, Olivier Sentieys, Steven Derrien. 209-216 [doi]
• Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous ArchitecturesMalgorzata Michalska, Nicolas Zufferey, Endri Bezati, Marco Mattavelli. 217-224 [doi]
• Distributed Dynamic Rate Adaptation on a Network on Chip with Traffic DistortionYves Durand, Christian Bernard, Fabien Clermidy. 225-232 [doi]
• Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core ProcessorZoran A. Salcic, Muhammad Nadeem, HeeJong Park, Jürgen Teich. 233-240 [doi]
• Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management StrategyJosé V. Escamilla, Mario R. Casu, Jose Flich. 241-248 [doi]
• Network Contention-Aware Method to Evaluate Data Coherency Protocols within a Compilation ToolchainLoïc Cudennec, Safae Dahmani, Guy Gogniat, Cédric Maignan, Martha Johanna Sepúlveda. 249-256 [doi]
• Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded Support for Multicore Processor SystemJoo On Ooi, Fawnizu Azmadi B. Hussin, Nordin Zakaria. 257-264 [doi]
• Pushing the Limits of Online Auto-Tuning: Machine Code Optimization in Short-Running KernelsFernando Akira Endo, Damien Couroussé, Henri-Pierre Charles. 265-272 [doi]
• Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core ArchitecturesLars Middendorf, Christian Haubelt. 273-280 [doi]
• Why Comparing System-Level MPSoC Mapping Approaches is Difficult: A Case StudyAndres Goens, Robert Khasanov, Jerónimo Castrillón, Simon Polstra, Andy D. Pimentel. 281-288 [doi]
• Programming Models and Methods for Heterogeneous Parallel Embedded SystemsSimone Casale Brunet, Endri Bezati, Marco Mattavelli. 289-296 [doi]
• The ForeC Synchronous Deterministic Parallel Programming Language for MulticoresEugene Yip, Alain Girault, Partha S. Roop, Morteza Biglari-Abhari. 297-304 [doi]
• Portable Multicore Resource Management for Applications with Performance ConstraintsConnor Imes, David H. K. Kim, Martina Maggio, Henry Hoffmann. 305-312 [doi]
• Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive ComputingJürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner, Stefan Wildermann. 313-320 [doi]
• Constructing Time-Predictable MPSoCs: Avoid Conflicts in Temporal ControlPeter P. Puschner, Bekim Cilku, Daniel Prokesch. 321-328 [doi]
• Faster Method for Tuning the Tile Size for Tile Matrix DecompositionTomohiro Suzuki. 329-336 [doi]
• On Constructing Cost Models for Online Automatic Tuning Using ATMathCoreLib: Case Studies through the SVD Computation on a Multicore ProcessorSeiji Nagashima, Takeshi Fukaya, Yusaku Yamamoto. 345-352 [doi]
• Autotuning of a Cut-Off for Task Parallel ProgramsShintaro Iwasaki, Kenjiro Taura. 353-360 [doi]
• A Performance Model and Efficiency-Based Assignment of Buffering Strategies for Automatic GPU Stencil Code GenerationYue Hu, David M. Koppelman, Steven R. Brandt. 361-368 [doi]
• Meta-programming and Multi-stage Programming for GPGPUsIan Masliah, Marc Baboulin, Joël Falcou. 369-376 [doi]
• Automatic Thread-Block Size Adjustment for Memory-Bound BLAS Kernels on GPUsDaichi Mukunoki, Toshiyuki Imamura, Daisuke Takahashi. 377-384 [doi]
• A Code Selection Mechanism Using Deep LearningHang Cui, Shoichi Hirasawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 385-392 [doi]