Abstract is missing.
- Games for formal design and verification of reactive systemsRajeev Alur. 3 [doi]
- Analyzing tabular requirements specifications using infinite state model checkingTevfik Bultan, Constance L. Heitmeyer. 7-16 [doi]
- Mixed symbolic representations for model checking software programsZijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic. 17-26 [doi]
- Component-based hardware/software co-verificationFei Xie, Guowu Yang, Xiaoyu Song. 27-36 [doi]
- A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-designHiren D. Patel, Sandeep K. Shukla, E. Mednick, Rishiyur S. Nikhil. 39-48 [doi]
- Low-power hardware synthesis from TRS-based specificationsGaurav Singh, Sandeep K. Shukla. 49-58 [doi]
- 802.11a transmitter: a case study in microarchitectural explorationNirav Dave, Michael Pellauer, S. Gerding, Arvind. 59-68 [doi]
- Automatic decomposition for sequential equivalence checking of system level and RTL descriptionsShobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu. 71-80 [doi]
- A verified development of hardware using CSP/spl par/BAlistair A. McEwan, Steve Schneider. 81 [doi]
- Panel: Nano-computing - do we need new formal approaches?M. Hsiao, S. Shukla, M. Gokhale, A. Lebeck. 85-86 [doi]
- Scalable program analysis using Boolean satisfiabilityAlexander Aiken. 89 [doi]
- Execution semantics and formalisms for multi-abstraction TLM assertionsWolfgang Ecker, Volkan Esen, Michael Hull. 93-102 [doi]
- A methodology for abstracting RTL designs into TL descriptionsNicola Bombieri, Franco Fummi, Graziano Pravadelli. 103-112 [doi]
- Using Reo for formal specification and verification of system designsNiloofar Razavi, Marjan Sirjani. 113-122 [doi]
- Programming models and languages for SoC-implemented architecturesR. Gupta. 125 [doi]
- Specifying and proving properties of timed I/O automata in the TIOA toolkitMyla Archer, Hongping Lim, Nancy A. Lynch, Sayan Mitra, Shinya Umeno. 129-138 [doi]
- Reliable design with multiple clock domainsE. Czeck, Ravi Nanavati, Joseph E. Stoy. 139-148 [doi]
- The SystemJ approach to system-level designFlavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic. 149-158 [doi]
- Integrating design and verification - from simple idea to practical systemC. Seger. 161 [doi]
- Efficient code generation from synchronous programsKlaus Schneider, Jens Brandt, Eric Vecchié. 165-174 [doi]
- Latency-insensitive design and central repetitive schedulingJulien Boucaron, Robert de Simone, Jean-Vivien Millo. 175-183 [doi]
- A scenario-aware data flow model for combined long-run average and worst-case performance analysisBart D. Theelen, Marc Geilen, Twan Basten, Jeroen Voeten, Stefan Valentin Gheorghita, Sander Stuijk. 185-194 [doi]
- Equivalence checking: a rule-based approachMasahiro Fujita, Subash Shankar, S. Shunsuke. 197 [doi]
- Formal methods for checking realizability of coalitions in 3-party systemsAnsuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti. 198 [doi]
- A semantic-driven synthesis flow for platform-based designQi Zhu, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli. 199 [doi]
- Assertion checking of control dominated systems with nonlinear solversIñigo Ugarte, Pablo Sanchez. 200 [doi]
- Compositional interaction specifications for SystemCFrederic Doucet, Ingolf Krüger, Rajesh K. Gupta, R. K. Shyamasundar. 201 [doi]
- R-SHIM: deterministic concurrency with recursion and shared variablesOlivier Tardieu, Stephen A. Edwards. 202 [doi]