Abstract is missing.
- Arithmetic Circuits Verification without Looking for Internal EquivalencesO. Sarbishei, Bijan Alizadeh, Masahiro Fujita. 7-16 [doi]
- From Data to Events: Checking Properties on the Control of a SystemChristophe Jacquet, Frédéric Boulanger, Dominique Marcadet. 17-26 [doi]
- Vacuity Analysis by Fault SimulationLuidi Di Guglielmo, Franco Fummi, Graziano Pravadelli. 27-36 [doi]
- Rule-Based Approaches for Equivalence Checking of SpecC ProgramsSubash Shankar, Masahiro Fujita. 39-48 [doi]
- Static Deadlock Detection for the SHIM Concurrent LanguageNalini Vasudevan, Stephen A. Edwards. 49-58 [doi]
- A Comparison of Two SystemC/TLM Semantics for Formal VerificationClaude Helmstetter, Olivier Ponsini. 59-68 [doi]
- Latency-Insensitive Hardware/Software InterfacesGreg Hoover, Forrest Brewer, Chris Gill. 71-72 [doi]
- Bisimulator 2.0: An On-the-Fly Equivalence Checker based on Boolean Equation SystemsRadu Mateescu, Emilie Oudot. 73-74 [doi]
- Assertion-Based Design with HorusYann Oddos, Katell Morin-Allory, Dominique Borrione. 75-76 [doi]
- A System Verilog Rewriting System for RTL Abstraction with Pentium Case StudySteve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang. 79-88 [doi]
- Directed-Logical Testing for Functional Verification of MicroprocessorsMichael Katelman, José Meseguer, Santiago Escobar. 89-100 [doi]
- Estimating the Performance of Cache Replacement PoliciesDaniel Grund, Jan Reineke. 101-112 [doi]
- Classification of General Data Flow Actors into Known Models of ComputationChristian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich. 119-128 [doi]
- On the Deterministic Multi-threaded Software Synthesis from Polychronous SpecificationsBijoy A. Jose, Sandeep K. Shukla, Hiren D. Patel, Jean-Pierre Talpin. 129-138 [doi]
- Virtual prototyping AADL architectures in a polychronous model of computationMa Yue, Jean-Pierre Talpin, Thierry Gautier. 139-148 [doi]
- MEMOCODE 2008 Co-Design ContestPatrick Schaumont, Krste Asanovic, James C. Hoe. 151-154 [doi]
- High-throughput Pipelined MergesortKermin Fleming, Myron King, Man Cheuk Ng, Asif Khan, Muralidaran Vijayaraghavan. 155-158 [doi]
- Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design ContestVJ Sananda. 159-162 [doi]
- H.264 Decoder: A Case Study in Multiple Design PointsKermin Fleming, Chun-Chieh Lin, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks. 165-174 [doi]
- Correctness of a Fault-Tolerant Real-Time Scheduler and its Hardware ImplementationEyad Alkassar, Peter Böhm, Steffen Knapp. 175-186 [doi]
- Specification and Verification of LambdaRAM: A Wide-area Distributed Cache for High Performance ComputingVenkatram Vishwanath, Lenore D. Zuck, Jason Leigh. 187-198 [doi]
- Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract)Arvind, Rishiyur S. Nikhil. 205-206 [doi]