Abstract is missing.
- Distributing C# methods and threads over Ethernet-connected FPGAs using KiwiDavid J. Greaves, Satnam Singh. 1-9 [doi]
- Rigorous system level modeling and analysis of mixed HW/SW systemsParaskevas Bourgos, Ananda Basu, Marius Bozga, Saddek Bensalem, Joseph Sifakis, Kai Huang. 11-20 [doi]
- Polychronous controller synthesis from MARTE CCSL timing specificationsHuafeng Yu, Jean-Pierre Talpin, Loïc Besnard, Thierry Gautier, Hervé Marchand, Paul Le Guernic. 21-30 [doi]
- Controller synthesis for pipelined circuits using uninterpreted functionsGeorg Hofferek, Roderick Bloem. 31-42 [doi]
- Mining assumptions for synthesisWenchao Li, Lili Dworkin, Sanjit A. Seshia. 43-50 [doi]
- Formal modelling and transformations of processor instruction setsAndrey Mokhov, Danil Sokolov, Maxim Rykunov, Alex Yakovlev. 51-60 [doi]
- Verification of microarchitectural refinements in rule-based systemsNirav Dave, Michael Katelman, Myron King, Arvind, José Meseguer. 61-71 [doi]
- MEMOCODE 2011 Hardware/Software CoDesign Contest: NoC simulatorDerek Chiou. 73-76 [doi]
- Fast scalable FPGA-based Network-on-Chip simulation modelsMichael Papamichael. 77-82 [doi]
- GPU-based NoC simulatorMahdy Zolghadr, Koosha Mirhosseini, Saeid Gorgin, Abbas Nayebi. 83-88 [doi]
- A flexible formal verification framework for industrial scale validationAnna Slobodová, Jared Davis, Sol Swords, Warren A. Hunt Jr.. 89-97 [doi]
- Predictive analysis for detecting serializability violations through Trace SegmentationArnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta. 99-108 [doi]
- SMT based false causal loop detection during code synthesis from Polychronous specificationsBijoy A. Jose, Abdoulaye Gamatié, Julien Ouy, Sandeep K. Shukla. 109-118 [doi]
- Efficient deadlock detection for concurrent systemsSaddek Bensalem, Andreas Griesmayer, Axel Legay, Thanh-Hung Nguyen, Doron Peled. 119-129 [doi]
- Function interface models for hardware compilationDan R. Ghica. 131-142 [doi]
- Modern constraint solving by propagationChristopher Jefferson. 143 [doi]
- A case study of hardware software co-design in a consumer ASICMark Shand. 145-150 [doi]
- Reachability analysis for incomplete networks of Markov decision processesRalf Wimmer, Ernst Moritz Hahn, Holger Hermanns, Bernd Becker. 151-160 [doi]
- Transforming SystemC Transaction Level Models into UPPAAL timed automataPaula Herber, Marcel Pockrandt, Sabine Glesner. 161-170 [doi]
- Modeling of time in discrete-event simulation of systems-on-chipGiovanni Funchal, Matthieu Moy. 171-180 [doi]
- Parallel assertions for debugging parallel programsDaniel Schwartz-Narbonne, Feng Liu, Tarun Pondicherry, David I. August, Sharad Malik. 181-190 [doi]
- Automatic generation of assertions from system level design using data miningLingyi Liu, David Sheridan, Viraj Athavale, Shobha Vasudevan. 191-200 [doi]
- EFSM-based model-driven approach to concolic testing of system-level designGiuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli, Stefano Soffia. 201-209 [doi]