Abstract is missing.
- Static branch frequency and program profile analysisYoufeng Wu, James R. Larus. 1-11 [doi]
- Using branch handling hardware to support profile-driven optimizationThomas M. Conte, Burzin A. Patel, J. Stan Cox. 12-21 [doi]
- Branch classification: a new mechanism for improving branch predictor performancePo-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt. 22-31 [doi]
- Techniques for compressing program address tracesAndrew R. Pleszkun. 32-39 [doi]
- Height reduction of control recurrences for ILP processorsMichael S. Schlansker, Vinod Kathail, Sadun Anik. 40-51 [doi]
- Theoretical modeling of superscalar processor performanceDerek B. Noonburg, John Paul Shen. 52-62 [doi]
- Iterative modulo scheduling: an algorithm for software pipelining loopsB. Ramakrishna Rau. 63-74 [doi]
- Minimum register requirements for a modulo scheduleAlexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham. 75-84 [doi]
- Minimizing register requirements under resource-constrained rate-optimal software pipeliningRamaswamy Govindarajan, Erik R. Altman, Guang R. Gao. 85-94 [doi]
- Software pipelining with register allocation and spillingJian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis. 95-99 [doi]
- Reducing memory traffic with CRegsPeter Dahl, Matthew T. O Keefe. 100-104 [doi]
- Dynamic memory disambiguation for array referencesDavid Bernstein, Doron Cohen, Dror E. Maydan. 105-111 [doi]
- A study of pointer aliasing for software pipelining using run-time disambiguationBogong Su, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu. 112-117 [doi]
- Data relocation and prefetching for programs with large data setsYoji Yamada, John Gyllenhall, Grant Haab, Wen-mei W. Hwu. 118-127 [doi]
- Cache designs with partial address matchingLishing Liu. 128-136 [doi]
- Minimizing branch misprediction penalties for superpipelined processorsChing-Long Su, Alvin M. Despain. 138-142 [doi]
- Facilitating superscalar processing via a combined static/dynamic register renaming schemeEric Sprangle, Yale N. Patt. 143-147 [doi]
- Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distributionRaymond Lo, Sun Chan, Fred C. Chow, Shin-Ming Liu. 148-152 [doi]
- A comparison of two pipeline organizationsMichael Golden, Trevor N. Mudge. 153-161 [doi]
- A fill-unit approach to multiple instruction issueManoj Franklin, Mark Smotherman. 162-171 [doi]
- A high-performance microarchitecture with hardware-programmable functional unitsRahul Razdan, Michael D. Smith. 172-180 [doi]
- The anatomy of the register file in a multiscalar processorScott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi. 181-190 [doi]
- Register file port requirements of transport triggered architecturesJan Hoogerbrugge, Henk Corporaal. 191-195 [doi]
- The effects of predicated execution on branch predictionGary S. Tyson. 196-206 [doi]
- Analysis of the conditional skip instructions of the HP precision architectureJonathan P. Vogel, Bruce K. Holmer. 207-216 [doi]
- Characterizing the impact of predicated execution on branch predictionScott A. Mahlke, Richard E. Hank, Roger A. Bringmann, John C. Gyllenhaal, David M. Gallagher, Wen-mei W. Hwu. 217-227 [doi]
- The effect of speculatively updating branch history on branch prediction accuracy, revisitedEric Hao, Po-Yung Chang, Yale N. Patt. 228-232 [doi]