Table of Contents

• Scalable Speculative Parallelization on Commodity ClustersHanjun Kim, Arun Raman, Feng Liu, Jae W. Lee, David I. August. 3-14 [doi]
• Hardware Support for Relaxed Concurrency Control in Transactional MemoryUtku Aydonat, Tarek S. Abdelrahman. 15-26 [doi]
• A Dynamically Adaptable Hardware Transactional MemoryMarc Lupon, Grigorios Magklis, Antonio González. 27-38 [doi]
• ASF: AMD64 Extension for Lock-Free Data Structures and Transactional MemoryJae Woong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth, David Christie, Dan Grossman. 39-50 [doi]
• Memory Latency Reduction via Thread ThrottlingHsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang. 53-64 [doi]
• Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access BehaviorYoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter. 65-76 [doi]
• Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread SchedulingVijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks. 77-88 [doi]
• Task Superscalar: An Out-of-Order Task PipelineYoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero. 89-100 [doi]
• Combating Aging with the Colt Duty Cycle EqualizerErika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko H. Lipasti. 103-114 [doi]
• SAFER: Stuck-At-Fault Error Recovery for MemoriesNak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee. 115-124 [doi]
• AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft ErrorsArun A. Nair, Lizy Kurian John, Lieven Eeckhout. 125-136 [doi]
• Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable FabricDaniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh. 137-148 [doi]
• Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management PoliciesAamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer. 151-162 [doi]
• STEM: Spatiotemporal Management of Capacity for Intra-core Last Level CachesDongyuan Zhan, Hong Jiang, Sharad C. Seth. 163-174 [doi]
• Sampling Dead Block Prediction for Last-Level CachesSamira Manabi Khan, Yingying Tian, Daniel A. Jiménez. 175-186 [doi]
• The ZCache: Decoupling Ways and AssociativityDaniel Sanchez, Christos Kozyrakis. 187-198 [doi]
• Efficient Selection of Vector Instructions Using Dynamic ProgrammingRajkishore Barik, Jisheng Zhao, Vivek Sarkar. 201-212 [doi]
• Many-Thread Aware Prefetching Mechanisms for GPGPU ApplicationsJaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard W. Vuduc. 213-224 [doi]
• Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai. 225-236 [doi]
• Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-KernelsMichael Steffen, Joseph Zambreno. 237-248 [doi]
• InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental HashingAdrian Nistor, Darko Marinov, Josep Torrellas. 251-262 [doi]
• Tolerating Concurrency Bugs Using Transactions as LifeguardsJie Yu, Satish Narayanasamy. 263-274 [doi]
• Architectural Support for Fair Reader-Writer LockingEnrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero. 275-286 [doi]
• AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation DetectionAbdullah Muzahid, Norimasa Otsuki, Josep Torrellas. 287-297 [doi]
• Register Cache System Not for Latency Reduction PurposeRyota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai. 301-312 [doi]
• Synergistic TLBs for High Performance Address Translation in Chip MultiprocessorsShekhar Srikantaiah, Mahmut T. Kandemir. 313-324 [doi]
• Erasing Core Boundaries for Robust and Configurable PerformanceShantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke. 325-336 [doi]
• Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded ProcessorsGuoping Long, Diana Franklin, Susmit Biswas, Pablo J. Ortiz, Jason Oberg, Dongrui Fan, Frederic T. Chong. 337-348 [doi]
• Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold CachesTimothy N. Miller, Renji Thomas, James Dinan, Bruce M. Adcock, Radu Teodorescu. 351-362 [doi]
• Understanding the Energy Consumption of Dynamic Random Access MemoriesThomas Vogelsang. 363-374 [doi]
• Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density MemoryJeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John. 375-384 [doi]
• Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile MemoriesAdrian M. Caulfield, Arup De, Joel Coburn, Todor I. Mollow, Rajesh K. Gupta, Steven Swanson. 385-395 [doi]
• Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection NetworksMinseon Ahn, Eun Jung Kim. 399-408 [doi]
• LOFT: A High Performance Network-on-Chip Providing Quality-of-Service SupportJin Ouyang, Yuan Xie. 409-420 [doi]
• Throughput-Effective On-Chip Networks for Manycore AcceleratorsAli Bakhoda, John Kim, Tor M. Aamodt. 421-432 [doi]
• Adaptive Flow Control for Robust Performance and EnergySyed Ali Raza Jafri, Yu-Ju Hong, Mithuna Thottethodi, T. N. Vijaykumar. 433-444 [doi]
• ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy EnvironmentXuehai Qian, Wonsun Ahn, Josep Torrellas. 447-458 [doi]
• Virtual Snooping: Filtering Snoops in Virtualized Multi-coresDaehoon Kim, Hwanju Kim, Jaehyuk Huh. 459-470 [doi]
• Fractal Coherence: Scalably Verifiable Cache CoherenceMeng Zhang, Alvin R. Lebeck, Daniel J. Sorin. 471-482 [doi]
• A Predictive Model for Dynamic Microarchitectural Adaptivity ControlChristophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Michael F. P. O Boyle. 485-496 [doi]
• ReMAP: A Reconfigurable Heterogeneous Multicore ArchitectureMatthew A. Watkins, David H. Albonesi. 497-508 [doi]
• Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPsMichael M. Lee, John Kim, Dennis Abts, Michael R. Marty, Jae W. Lee. 509-519 [doi]
• Adaptive and Speculative Slack Simulations of CMPs on CMPsJianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, Murali Annavaram, Michel Dubois. 523-534 [doi]
• SD3: A Scalable Approach to Dynamic Data-Dependence ProfilingMinjang Kim, Hyesoon Kim, Chi-Keung Luk. 535-546 [doi]
• Automatic Parallelization in a Binary RewriterAparna Kotha, Kapil Anand, Matthew Smithson, Greeshma Yellareddy, Rajeev Barua. 547-557 [doi]