Table of Contents

• Keynote 1 NoCs: It is about the memory and the programming modelIvo Bolsens. 1 [doi]
• HiRA: A methodology for deadlock free routing in hierarchical networks on chipRickard Holsmark, Shashi Kumar, Maurizio Palesi, Andres Mejia. 2-11 [doi]
• Using adaptive routing to compensate for performance heterogeneityYury Markovsky, Yatish Patel, John Wawrzynek. 12-21 [doi]
• Fault-tolerant architecture and deflection routing for degradable NoC switchesAdan Kohler, Martin Radetzki. 22-31 [doi]
• Adaptive stochastic routing in fault-tolerant on-chip networksWei Song, Doug Edwards, Jose Luis Nunez-Yanez, Sohini Dasgupta. 32-37 [doi]
• Static virtual channel allocation in oblivious routingKeun Sup Shim, Myong Hyon Cho, Michel A. Kinsy, Tina Wen, Mieszko Lis, G. Edward Suh, Srinivas Devadas. 38-43 [doi]
• Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chipYue Qian, Zhonghai Lu, Wenhua Dou. 44-53 [doi]
• Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect linksBo Fu, David Wolpert, Paul Ampadu. 54-63 [doi]
• Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-ChipLei Wang, Yuho Jin, HyungJun Kim, Eun Jung Kim. 64-73 [doi]
• Analytical modeling and evaluation of On-Chip Interconnects using Network CalculusMohamed Bakhouya, Suboh A. Suboh, Jaafar Gaber, Tarek A. El-Ghazawi. 74-79 [doi]
• Energy efficient application mapping to NoC processing elements operating at multiple voltage levelsPavel Ghosh, Arunabha Sen, Alexander Hall. 80-85 [doi]
• The design of a latency constrained, power optimized NoC for a 4G SoCRudy Beraha, Isask har Walter, Israel Cidon, Avinoam Kolodny. 86 [doi]
• Performance Evaluation of NoC Architectures for Parallel WorkloadsHenrique C. Freitas, Marco A. Z. Alves, Lucas Mello Schnorr, Philippe Olivier Alexandre Navaux. 87 [doi]
• Packet-level static timing analysis for NoCsEvgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask har Walter. 88 [doi]
• Increasing NoC power estimation accuracy through a rate-based modelGuilherme Guindani, Cezar Reinbrecht, Thiago R. da Rosa, Fernando Moraes. 89 [doi]
• On-Chip photonic interconnects for scalable multi-core architecturesAvinash Karanth Kodi, Randy Morris, Ahmed Louri, Xiang Zhang. 90 [doi]
• A Modeling and exploration framework for interconnect network design in the nanometer eraAjay Joshi, Fred Chen, Vladimir Stojanovic. 91 [doi]
• Power reduction through physical placement of asynchronous routersDaniel Gebhardt, Kenneth S. Stevens. 92 [doi]
• Networks-on-chip in emerging interconnect paradigms: Advantages and challengesLuca P. Carloni, Partha Pande, Yuan Xie. 93-102 [doi]
• Keynote 2 NoC s at the center of chip architecture: Urgent needs (today) and what they must become (future)Andrew Chien. 103 [doi]
• Analysis of photonic networks for a chip multiprocessor using scientific applicationsGilbert Hendry, Shoaib Kamil, Aleksandr Biberman, Johnnie Chan, Benjamin G. Lee, Marghoob Mohiyuddin, Ankit Jain, Keren Bergman, Luca P. Carloni, John Kubiatowicz, Leonid Oliker, John Shalf. 104-113 [doi]
• Scalability of network-on-chip communication architecture for 3-D meshesAwet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen. 114-123 [doi]
• Silicon-photonic clos networks for global on-chip communicationAjay Joshi, Christopher Batten, Yong Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanovic, Vladimir Stojanovic. 124-133 [doi]
• Contention-free on-chip routing of optical packetsSomayyeh Koohi, Shaahin Hessabi. 134-143 [doi]
• Connection-centric network for spiking neural networksRobin Emery, Alexandre Yakovlev, E. Graeme Chester. 144-152 [doi]
• A Communication and configuration controller for NoC based reconfigurable data flow architectureFabien Clermidy, Romain Lemaire, Yvain Thonnart, Pascal Vivet. 153-162 [doi]
• Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regionsMartti Forsell. 163-172 [doi]
• Best of both worlds: A bus enhanced NoC (BENoC)Ran Manevich, Isask har Walter, Israel Cidon, Avinoam Kolodny. 173-182 [doi]
• Flow-aware allocation for on-chip networksArnab Banerjee, Simon W. Moore. 183-192 [doi]
• CTC: An end-to-end flow control protocol for multi-core systems-on-chipNicola Concer, Luciano Bononi, Michael Soulie, Riccardo Locatelli, Luca P. Carloni. 193-202 [doi]
• Performance and power efficient on-chip communication using adaptive virtual point-to-point connectionsMehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol. 203-212 [doi]
• Keynote 3 (Banquet Talk) Digital spaceAnant Agarwal. 213 [doi]
• A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection networkAnh T. Tran, Dean Truong, Bevan M. Baas. 214-223 [doi]
• A modular synchronizing FIFO for NoCsTarik Ono-Tesfaye, Mark R. Greenstreet. 224-233 [doi]
• Estimating reliability and throughput of source-synchronous wave-pipelined interconnectPaul Teehan, Guy G. Lemieux, Mark R. Greenstreet. 234-243 [doi]
• Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architectureDaniele Ludovici, Alessandro Strano, Davide Bertozzi, Luca Benini, Georgi Gaydadjiev. 244-249 [doi]
• Dynamic packet fragmentation for increased virtual channel utilization in on-chip routersYoung Hoon Kang, Taek-Jun Kwon, Jeff Draper. 250-255 [doi]
• Diagnosis of interconnect shorts in mesh NoCsMarcos Herve, Érika F. Cota, Fernanda Lima Kastensmidt, Marcelo Lubaszewski. 256-265 [doi]
• BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channelYing-Cherng Lan, Shih-Hsin Lo, Yueh-Chi Lin, Yu Hen Hu, Sao-Jie Chen. 266-275 [doi]
• Exploring concentration and channel slicing in on-chip network routerPrabhat Kumar, Yan Pan, John Kim, Gokhan Memik, Alok N. Choudhary. 276-285 [doi]
• Author index286-287 [doi]