Table of Contents

• System-Level Application-Specific NoC Design for Network and Multimedia ApplicationsLazaros Papadopoulos, Dimitrios Soudris. 1-9 [doi]
• Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive MeasurementsNicolas Fournel, Antoine Fraboulet, Paul Feautrier. 10-19 [doi]
• A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable PlatformsIoannis Panagopoulos, Christos Pavlatos, George Manis, George K. Papakonstantinou. 20-30 [doi]
• An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC ArchitectureJulien Delorme. 31-42 [doi]
• Template Vertical Dictionary-Based Program Compression Scheme on the TTAMing-che Lai, Zhiying Wang, Jianjun Guo, Kui Dai, Shen Li. 43-52 [doi]
• Asynchronous Functional Coupling for Low Power Sensor Network ProcessorsDelong Shang, Chi-Hoon Shin, Ping Wang, Fei Xia, Albert Koelmans, Myeong-Hoon Oh, Seongwoon Kim, Alexandre Yakovlev. 53-63 [doi]
• A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential DesignsNoureddine Chabini. 64-74 [doi]
• Low-Power Content Addressable Memory With Read/Write and Matched Mask PortsSaleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt. 75-85 [doi]
• The Design and Implementation of a Power Efficient Embedded SRAMYijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li. 86-96 [doi]
• Design of a Linear Power Amplifier with +/-1.5V Power Supply Using ALADINBjörn Lipka, Ulrich Kleine. 97-106 [doi]
• Settling Time Minimization of Operational AmplifiersAndrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo. 107-116 [doi]
• Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTsCosmin Popa. 117-124 [doi]
• Computation of Joint Timing Yield of Sequential Networks Considering Process VariationsAmit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula. 125-137 [doi]
• A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin EvaluationV. Migairou, Robin Wilson, S. Engels, Zequin Wu, Nadine Azémard, Philippe Maurine. 138-147 [doi]
• A Statistical Approach to the Timing-Yield Optimization of Pipeline CircuitsChin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang. 148-159 [doi]
• A Novel Gate-Level NBTI Delay Degradation Model with Stacking EffectHong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. 160-170 [doi]
• Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-ComponentsMarko Hoyer, Domenik Helms, Wolfgang Nebel. 171-180 [doi]
• Logic Style Comparison for Ultra Low Power Operation in 65nm TechnologyMandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija. 181-190 [doi]
• Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI DegradationC. R. Parthasarathy, A. Bravaix, C. Guérin, M. Denais, V. Huard. 191-200 [doi]
• Clock Distribution Techniques for Low-EMI DesignDavide Pandini, Guido A. Repetto, Vincenzo Sinisi. 201-210 [doi]
• Crosstalk Waveform Modeling Using Wave FittingMini Nanua, David Blaauw. 211-221 [doi]
• Weakness Identification for Effective Repair of Power Distribution NetworkTakashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu. 222-231 [doi]
• New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip BusesPrassanna Sithambaram, Alberto Macii, Enrico Macii. 232-241 [doi]
• On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron InterconnectsTudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner. 242-254 [doi]
• Soft Error-Aware Power Optimization Using Gate SizingFoad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh. 255-267 [doi]
• Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile DevicesMatthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, Andreas Mühlberger. 268-277 [doi]
• RTL Power Modeling and Estimation of Sleep Transistor Based Power GatingSven Rosinger, Domenik Helms, Wolfgang Nebel. 278-287 [doi]
• Functional Verification of Low Power Designs at RTLAllan Crone, Gabriel Chidolue. 288-299 [doi]
• XEEMU: An Improved XScale Power SimulatorZoltán Herczeg, Ákos Kiss, Daniel Schmidt, Norbert Wehn, Tibor Gyimóthy. 300-309 [doi]
• Low Power Elliptic Curve CryptographyMaurice Keller, William P. Marnane. 310-319 [doi]
• Design and Test of Self-checking Asynchronous Control CircuitJian Ruan, Zhiying Wang, Kui Dai, Yong Li. 320-329 [doi]
• An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-ChipsBehnam Ghavami, Hossein Pedram. 330-339 [doi]
• Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPAAlin Razafindraibe, Michel Robert, Philippe Maurine. 340-351 [doi]
• Performance Optimization of Embedded Applications in a Hybrid Reconfigurable PlatformMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. 352-362 [doi]
• The Energy Scalability of Wavelet-Based, Scalable Video DecodingHendrik Eeckhaut, Harald Devos, Dirk Stroobandt. 363-372 [doi]
• Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy ConsumptionMiguel Peon-Quiros, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris. 373-383 [doi]
• Exploiting Input Variations for Energy ReductionToshinori Sato, Yuji Kunitake. 384-393 [doi]
• A Model of DPA Syndrome and Its Application to the Identification of Leaking GatesAlin Razafindraibe, Philippe Maurine. 394-403 [doi]
• Static Power Consumption in CMOS Gates Using Independent BodiesDavid Guerrero, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo. 404-412 [doi]
• Moderate Inversion: Highlights for Low Voltage DesignFabrice Guigues, Edith Kussener, Benjamin Duval, Hervé Barthélemy. 413-422 [doi]
• On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time SystemsNaotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui. 423-432 [doi]
• Semi Custom Design: A Case Study on SIMD ShufflersPraveen Raghavan, Nandhavel Sethubalasubramanian, Satyakiran Munaga, Estela Rey Ramos, Murali Jayapala, Oliver Weiss, Francky Catthoor, Diederik Verkest. 433-442 [doi]
• Optimization for Real-Time Systems with Non-convex Power Versus Speed ModelsAni Nahapetian, Foad Dabiri, Miodrag Potkonjak, Majid Sarrafzadeh. 443-452 [doi]
• Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOSHarry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki. 453-462 [doi]
• A Fast and Accurate Power Estimation Methodology for QDI Asynchronous CircuitsBehnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram. 463-473 [doi]
• Subthreshold Leakage Modeling and Estimation of General CMOS Complex GatesPaulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas. 474-484 [doi]
• A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW PartitioningChristophe Lucarz, Marco Mattavelli. 485-494 [doi]
• Fast Calculation of Permissible Slowdown Factors for Hard Real-Time SystemsHenrik Lipskoch, Karsten Albers, Frank Slomka. 495-504 [doi]
• Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss RateNikolas Kroupis, Dimitrios Soudris. 505-515 [doi]
• A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip VariationsFrancesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti. 516-525 [doi]
• Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input DataOscar Gustafsson, Saeeid Tahmasbi Oskuii, Kenny Johansson, Per Gunnar Kjeldsberg. 526-535 [doi]
• Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power SupplyJon Alfredsson, Snorre Aunet. 536-545 [doi]
• Low-Power Digital Filtering Based on the Logarithmic Number SystemCharalambos Basetas, Ioannis Kouretas, Vassilis Paliouras. 546-555 [doi]
• A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage ScalingSylvain Miermont, Pascal Vivet, Marc Renaudin. 556-565 [doi]
• Dependability Evaluation of Time-Redundancy Techniques in Integer MultipliersHenrik Eriksson. 566-575 [doi]
• Design and Industrialization Challenges of Memory Dominated SOCsJ. M. Daga. 576 [doi]
• Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer TechnologiesDavide Pandini. 577 [doi]
• Analog Power ModellingC. Svensson. 578 [doi]
• Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone PlatformsF. Dahlgren. 579 [doi]
• System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving ParametersA. Emrich. 580 [doi]