Table of Contents

• Subthreshold FIR Filter Architecture for Ultra Low Power ApplicationsBiswajit Mishra, Bashir M. Al-Hashimi. 1-10 [doi]
• Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold DesignsBahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici. 11-20 [doi]
• Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic CircuitsArmin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici. 21-30 [doi]
• Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage ReductionMatteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi. 31-41 [doi]
• Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-GatingAshoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 42-51 [doi]
• Intelligate: Scalable Dynamic Invariant Learning for Power ReductionRoni Wiener, Gila Kamhi, Moshe Y. Vardi. 52-61 [doi]
• Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power ConsumptionMasanori Muroyama, Tohru Ishihara, Hiroto Yasuura. 62-71 [doi]
• Power-Aware Design via Micro-architectural Link to ImplementationYoni Aizik, Gila Kamhi, Yael Zbar, Hadas Ronen, Muhammad Abozaed. 72-81 [doi]
• Untraditional Approach to Computer Energy ReductionVasily G. Moshnyaga. 82-92 [doi]
• Mixed Radix-2 and High-Radix RNS Bases for Low-Power MultiplicationIoannis Kouretas, Vassilis Paliouras. 93-102 [doi]
• Power Optimization of Parallel Multipliers in Systems with Variable Word-LengthSaeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki. 103-115 [doi]
• A Design Space Comparison of 6T and 8T SRAM Core-CellsFlorian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel. 116-125 [doi]
• Latched CMOS DRAM Sense Amplifier Yield Analysis and OptimizationYan Li, Helmut Schneider, Florian Schnabel, Roland Thewes, Doris Schmitt-Landsiedel. 126-135 [doi]
• Understanding the Effect of Intradie Random Process Variations in Nanometer Domino LogicMassimo Alioto, Gaetano Palumbo, Melita Pennisi. 136-145 [doi]
• A Study on CMOS Time Uncertainty with Technology ScalingMonica Figueiredo, Rui L. Aguiar. 146-155 [doi]
• Static Timing Model Extraction for Combinational CircuitsBing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann. 156-166 [doi]
• A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTAWalter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann. 167-177 [doi]
• Statistical Modeling and Analysis of Static Leakage and Dynamic Switching PowerHoward Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah. 178-187 [doi]
• Logic Synthesis of Handshake Components Using Structural Clustering TechniquesFrancisco Fernández-Nogueira, Josep Carmona. 188-198 [doi]
• Fast Universal SynchronizersRostislav (Reuven) Dobkin, Ran Ginosar. 199-208 [doi]
• A Performance-Driven Multilevel Framework for the X-Based Full-Chip RouterTsung-Yi Ho. 209-218 [doi]
• PMD: A Low-Power Code for Networks-on-Chip Based on Virtual ChannelsAlberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner. 219-228 [doi]
• Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated CircuitsThomas Ordas, Mathieu Lisart, Etienne Sicard, Philippe Maurine, Lionel Torres. 229-236 [doi]
• A Comparison between Two Logic Synthesis Forms from Digital Switching Noise ViewpointGiorgio Boselli, Valentina Ciriani, Valentino Liberali, Gabriella Trucco. 237-246 [doi]
• Generating Worst-Case Stimuli for Accurate Power Grid AnalysisPedro Marques Morgado, Paulo F. Flores, José C. Monteiro, Luis Miguel Silveira. 247-257 [doi]
• Monolithic Multi-mode DC-DC Converter with Gate Voltage OptimizationNuno Dias, Marcelino Santos, Floriberto Lima, Beatriz Borges, Júlio Paisana. 258-267 [doi]
• Energy Efficiency of Power-Gating in Low-Power Clocked Storage ElementsChristophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija. 268-276 [doi]
• A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy DissipationFabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo. 277-286 [doi]
• Energy Efficient Elliptic Curve ProcessorMaurice Keller, William P. Marnane. 287-296 [doi]
• Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal ProcessingMarco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala. 297-306 [doi]
• Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable ArchitecturesDmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich. 307-317 [doi]
• Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller AmplifiersAndrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo. 318-327 [doi]
• Ultra Low Voltage High Speed Differential CMOS InverterOmid Mirmotahari, Yngvar Berg. 328-337 [doi]
• Differential Capacitance AnalysisMarco Bucci, Raimondo Luzzi, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti. 338-347 [doi]
• Automated Synchronous-to-Asynchronous Circuits Conversion: A SurveyMartin Simlastík, Viera Stopjaková. 348-358 [doi]
• Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip BusesAntoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien. 359-368 [doi]
• Analytical High-Level Power Model for LUT-Based ComponentsRuzica Jevtic, Carlos Carreras. 369-378 [doi]
• A Formal Approach for Estimating Embedded System Execution Time and Energy ConsumptionGustavo Rau de Almeida Callou, Paulo Romero Martins Maciel, Ermeson Carneiro de Andrade, Bruno Costa e Silva Nogueira, Eduardo Tavares, Meuse N. Oliveira Jr.. 379-388 [doi]
• Power Dissipation Associated to Internal Effect Transitions in Static CMOS GatesAlejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo. 389-398 [doi]
• Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer LevelFelipe Machado, Teresa Riesgo, Yago Torroja. 399-408 [doi]
• Data Dependence of Delay Distribution for a Planar BusFrancesc Moll, Joan Figueras, Antonio Rubio. 409-418 [doi]
• Towards Novel Approaches in Design Automation for FPGA Power OptimizationJuanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker. 419-428 [doi]
• Smart Enumeration: A Systematic Approach to Exhaustive SearchTim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk. 429-438 [doi]
• An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAsKostas Siozios, Dimitrios Soudris. 439-448 [doi]
• Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array ProcessorMladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest. 449-457 [doi]
• Integration of Power Management Units onto the SoCFloriberto Lima. 458 [doi]
• Model to Hardware Matching for nm Scale TechnologiesSani R. Nassif. 459 [doi]
• Power and Profit: Engineering in the EnvelopeTed Vucurevic. 460 [doi]