Abstract is missing.
- A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoCTanguy Sassolas, Nicolas Ventroux, Nassima Boudouani, Guillaume Blanc. 1-10 [doi]
- An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedded SoftwareChristian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiß, Josef Haid. 11-20 [doi]
- System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and CrosstalkMartin Gag, Tim Wegner, Dirk Timmermann. 21-30 [doi]
- Residue Arithmetic for Designing Low-Power Multiply-Add UnitsIoannis Kouretas, Vassilis Paliouras. 31-40 [doi]
- An On-Chip Flip-Flop Characterization CircuitAbhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi. 41-50 [doi]
- A Low-Voltage Log-Domain Integrator Using MOSFET in Weak InversionLida Ramezani. 51-61 [doi]
- Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI CircuitsMassimo Alioto, Elio Consoli, Gaetano Palumbo. 62-72 [doi]
- A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis FrameworkDimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi. 73-83 [doi]
- An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAsCristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José C. Monteiro. 84-93 [doi]
- On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFSPascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh. 94-104 [doi]
- Self-Timed SRAM for Energy Harvesting SystemsAbdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev. 105-115 [doi]
- L1 Data Cache Power Reduction Using a Forwarding PredictorP. Carazo, R. Apolloni, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado. 116-125 [doi]
- Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process VariationsMohsen Raji, Alireza Tajary, Behnam Ghavami, Hossein Pedram, Hamid R. Zarandi. 126-136 [doi]
- Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring CaseOussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet. 137-149 [doi]
- Hermes-A - An Asynchronous NoC Router with Distributed RoutingJulian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans. 150-159 [doi]
- Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-ChipAlberto García Ortiz, Leandro Soares Indrusiak. 160-169 [doi]
- Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random V::T:: Variations on TimingBahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici. 170-179 [doi]
- Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative AnalysisMarco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello. 180-189 [doi]
- Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process VariationsQin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs. 190-199 [doi]
- White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing SimulationChristoph Knoth, Irina Eichwald, Petra Nordholz, Ulf Schlichtmann. 200-210 [doi]
- Controlled-Precision Pure-Digital Square-Wave Frequency SynthesizerAbdelkrim Kamel Oudjida, Ahmed Liacha, Mohamed Lamine Berrandjia, Rachid Tiar. 211-217 [doi]
- An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock SynthesisOliver Schrape, Frank Winkler, Steffen Zeidler, Markus Petri, Eckhard Grass, Ulrich Jagdhold. 218-227 [doi]
- Clock Network Synthesis with Concurrent Gate InsertionJingwei Lu, Wing-Kai Chow, Chiu-Wing Sham. 228-237 [doi]
- Modeling Time Domain Magnetic Emissions of ICsVictor Lomné, Philippe Maurine, Lionel Torres, Thomas Ordas, Mathieu Lisart, Jérome Toublanc. 238-249 [doi]
- Power Profiling of Embedded Analog/Mixed-Signal SystemsJan Haase, Christoph Grimm. 250 [doi]
- Open-People: Open Power and Energy Optimization PLatform and EstimatorDaniel Chillet. 251 [doi]
- Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMSFrançois Pêcheux, Khouloud Zine el Abidine, Alain Greiner. 252 [doi]
- ASTEC: Asynchronous Technology for Low Power and Secured Embedded SystemsMarc Renaudin. 253 [doi]
- OPENTLM and SOCKET: Creating an Open EcoSystem for Virtual Prototyping of Complex SOCsLaurent Maillet-Contoz. 254 [doi]
- Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIsKiyoo Itoh. 255 [doi]
- 3D Integration for Digital and Imagers Circuits: Opportunities and ChallengesMarc Belleville. 256 [doi]
- Signing Off Industrial Designs on Evolving TechnologiesSébastien Marchal. 257 [doi]