Table of Contents

• Mixed-grained reconfigurable architecture supporting flexible reliability and C-based designHiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye. 1-6 [doi]
• SoC self-integration mechanism for dynamic reconfigurable systems based on collaborative macro-function unitsVictor Dumitriu, Lev Kirischian. 1-7 [doi]
• A single-chip solution for the secure remote configuration of FPGAs using bitstream compressionJo Vliegen, Nele Mentens, Ingrid Verbauwhede. 1-6 [doi]
• Distributed execution of transmural electrophysiological imaging with CPU, GPU, and FPGASam Skalicky, Sonia López, Marcin Lukowiak. 1-7 [doi]
• Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA acceleratorKeisuke Dohi, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri. 1-6 [doi]
• Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platformGarbi Singla, Félix Tobajas, Valentin de Armas. 1-6 [doi]
• High level synthesis: Where are we? A case study on matrix multiplicationSam Skalicky, Christopher Wood, Marcin Lukowiak, Matthew Ryan. 1-7 [doi]
• Countermeasures against EM analysis for a secured FPGA-based AES implementationPaolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle. 1-6 [doi]
• A framework for PC applications with portable and scalable FPGA acceleratorsMarkus Weinhardt, Alexander Krieger, Thomas Kinder. 1-6 [doi]
• A low complexity H.264/AVC 4×4 intra prediction architecture with macroblock/block reorderingMilica Orlandic, Kjetil Svarstad. 1-6 [doi]
• Max-hashing fragments for large data sets detectionJean-Pierre David. 1-6 [doi]
• Timing error handling on CGRAsThomas Schweizer, Wolfgang Rosenstiel, Luigi Vaz Ferreira, Marcus Ritt. 1-6 [doi]
• Towards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysisByron Navas, Johnny Öberg, Ingo Sander. 1-6 [doi]
• PolyNOC - A polymorphic thread simulator for NoC communication based embedded systemsSwamy D. Ponpandi, Zhang Zhang, Akhilesh Tyagi. 1-8 [doi]
• Extracting memory-level parallelism through reconfigurable hardware tracesMingjie Lin, Shaoyi Cheng, John Wawrzynek. 1-8 [doi]
• Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graphBai Yu, Mohammed Alawad, Michael Riera, Mingjie Lin. 1-8 [doi]
• Improved method for parallel AES-GCM cores using FPGAsKarim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. 1-4 [doi]
• Parallel and configurable turbo decoder implementation for 3GPP-LTELuis F. Gonzalez-Perez, Lennin C. Yllescas-Calderon, Ramon Parra-Michel. 1-6 [doi]
• A reconfigurable architecture for searching optimal software code to implement block cipher permutation matricesElif Bilge Kavun, Gregor Leander, Tolga Yalçin. 1-8 [doi]
• Dynamic and partial reconfiguration of Zynq 7000 under LinuxMuhammed Al Kadi, Patrick Rudolph, Diana Göhringer, Michael Hübner. 1-5 [doi]
• Optimization techniques for a high level synthesis implementation of the Sobel filterJoshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings. 1-6 [doi]
• A platform for secure IP integration in Xilinx Virtex FPGAsAli Ebrahim, Khaled Benkrid, Jalal Khalifat, Chuan Hong. 1-6 [doi]
• 2: An open source framework for FPGA-GPU PCIe communicationYann Thoma, Alberto Dassatti, Daniel Molla. 1-6 [doi]
• A VLSI architecture for the QR decomposition based on the MCGR algorithmPedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García. 1-6 [doi]
• Dynamic simulation of direct torque control of induction motors with FPGA based acceleratorsHamed Sajjadi Kia, Mohammad A. Zare, Rejesh G. Kavasseri, Cristinel Ababei. 1-6 [doi]
• BSW: FPGA-accelerated BLAST-Wrapped Smith-Waterman alignerBryant C. Lam, Carlo Pascoe, Scott Schaecher, Herman Lam, Alan D. George. 1-7 [doi]
• Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocationJan Heisswolf, Maximilian Singh, Martin Kupper, Ralf König, Jürgen Becker. 1-8 [doi]
• A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systemsMichael Rückauer, Daniel M. Muñoz, Timo Stripf, Oliver Oey, Carlos H. Llanos, Jürgen Becker. 1-6 [doi]
• ModHDL: A modular and expandable language for developing synchronous hardwareFabian May, Friedrich Mayer-Lindenberg. 1-6 [doi]
• Design of asynchronous systems on FPGA using direct mapping and synchronous specificationDuarte L. Oliveira, Diego Bompean, Lester A. Faria, Joao Luis V. Oliveira. 1-6 [doi]
• Power efficiency benchmarking of a partially reconfigurable, many-tile system implemented on a Xilinx Virtex-6 FPGARaymond J. Weber, Justin A. Hogan, Brock J. LaMeres. 1-4 [doi]
• Improving FPGA placement with a self-organizing mapTimm Bostelmann, Sergei Sawitzki. 1-6 [doi]
• Improving calibration precision of signal-delay-based time measurement systems in FPGAsMatthias Hinkfoth, Ralf Joost, Ralf Salomon. 1-6 [doi]
• NoC-based hardware function libraries for running multiple DSP algorithmsB. I. Gea-Garcia, J. L. Vázquez-Avila, Remberto Sandoval-Arechiga, J. L. Pizano-Escalante, Ramon Parra-Michel, Mario Siller. 1-6 [doi]
• Design and implementation of a modular, low latency, fault-aware, FPGA-based network interfaceRoberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini. 1-6 [doi]
• Real-timerange image preprocessing on FPGAsMoritz Schmid, Markus Blocherer, Frank Hannig, Jürgen Teich. 1-8 [doi]
• Leakage power reduction in FPGA DSP circuits through algorithmic noise toleranceEdgar Mora-Sanchez, Jason Helge Anderson. 1-6 [doi]
• Processor arrays generation for matrix algorithms used in embedded platformsRoberto Perez-Andrade, Cesar Torres-Huitzil, René Cumplido, Juan M. Campos. 1-6 [doi]
• A hierarchical parallel evolvable hardware based on network on chipJun Rong Wang, Dan Wang, Jin-mei Lai. 1-6 [doi]
• Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq. 1-6 [doi]
• Efficient multilevel interconnect topology for cluster-based mesh FPGA architectureEmna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi. 1-6 [doi]
• Keynote 2 - Past, current, and future of faster, cheaper, betterTim Gallagher. 1 [doi]
• A scalable evolvable hardware processing arrayAngel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo. 1-7 [doi]
• The Hamiltonian-based odd-even turn model for adaptive routing in interconnection networksPoona Bahrebar, Dirk Stroobandt. 1-6 [doi]
• Numerically efficient and biophysically accurate neuroprocessing platformJuan Carlos Moctezuma, Joseph McGeehan, Jose Luis Nunez-Yanez. 1-6 [doi]
• Range tree-linked list hierarchical search structure for packet classification on FPGAsOguzhan Erdem, Aydin Carus. 1-6 [doi]
• Keynote 3 - Extreme scale challenges: Can reconfigurable computing come to the rescue?Maya Gokhale. 1 [doi]
• Energy-efficient large-scale matrix multiplication on FPGAsKiran Kumar Matam, Viktor K. Prasanna. 1-8 [doi]
• A restricted dynamically reconfigurable architecture for low power processorsTakeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura. 1-7 [doi]
• RALP: Reconvergence-aware layer partitioning for 3D FPGAsQingyu Liu, Yuchun Ma, Yu Wang 0002, Wayne Luk, Jinian Bian. 1-6 [doi]
• An effective window based legalization algorithm for FPGA placementYu Wang, Hyunchul Shin. 1-4 [doi]
• FPGA prototyping of large reconfigurable ADPLL network for distributed clock generationChuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko. 1-6 [doi]
• Accuracy, cost, and performance tradeoffs for floating-point accumulationKrishna K. Nagar, Jason D. Bakos. 1-4 [doi]
• Performance modeling of reconfigurable distributed systems based on the opensparc FPGA board and the SIRC communication frameworkKevin L. Thomas, Michael S. Thompson. 1-7 [doi]
• Enhancing productivity with back-end similarity matching of digital circuits for IP reuseKevin Zeng, Peter Athanas. 1-6 [doi]
• Exploring the problems of placement and mapping in NoC-based reconfizurable systemsJonas Gomes Filho, Wang Jiang Chau. 1-4 [doi]
• PASC: Physically authenticated stable-clocked soc platform on low-cost FPGAsAydin Aysu, Patrick Schaumont. 1-6 [doi]
• Tree-less Huffman coding algorithm for embedded systemsMarco Antonio Soto Hernandez, Oscar Alvarado Nava, Eduardo Rodriguez-Martinez, Francisco Javier Zaragoza Martínez. 1-6 [doi]
• Design of low area-overhead ring oscillator PUF with large challenge spaceDurga Prasad Sahoo, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty. 1-6 [doi]
• Programming FPGA based NoCs with JavaGary Plumbridge, Neil C. Audsley. 1-6 [doi]
• m)Guillaume Reymond, Victor Murillo. 1-6 [doi]
• Automated design flow for no-cost configuration error detection in sram-based FPGAsMohamed Ben Jrad, Régis Leveugle. 1-6 [doi]
• Lightweight and compact solutions for secure reconfiguration of FPGAsKarim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. 1-4 [doi]
• Loopy - An open-source TCP/IP rapid prototyping and validation frameworkChristian de Schryver, Philipp Schläfer, Norbert Wehn, Thomas Fischer, Arnd Poetzsch-Heffter. 1-6 [doi]
• Optimal mapping of multiple packet lookup schemes onto FPGASwapnil Haria, Viktor K. Prasanna. 1-8 [doi]
• Fast fixed-point divider based on Newton-Raphson method and piecewise polynomial approximationA. Rodriguez-Garcia, L. Pizano-Escalante, Ramon Parra-Michel, Omar Humberto Longoria-Gandara, Joaquín Cortez González. 1-6 [doi]
• A high performance architecture for computing burrows-wheeler transform on FPGAsUmer I. Cheema, Ashfaq A. Khokhar. 1-6 [doi]
• Very low resource table-based FPGA evaluation of elementary functionsHorácio C. Neto, Mário P. Véstias. 1-6 [doi]
• Alternative implementations of a fractional order control algorithm on FPGAsCristina I. Muresan, George Dan Mois, Silviu Folea, Clara M. Ionescu. 1-6 [doi]
• New universal element with integrated PUF and TRNG capabilityMichal Varchola, Milos Drutarovský, Viktor Fischer. 1-6 [doi]
• Energy-efficient architecture for stride permutation on streaming dataRen Chen, Viktor K. Prasanna. 1-7 [doi]
• A delay-based PUF design using multiplexer chainsMiaoqing Huang, Shiming Li. 1-6 [doi]
• Online heavy hitter detector on FPGADa Tong, Viktor K. Prasanna. 1-6 [doi]
• Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoCZoltán Endre Rákossy, Axel Acosta Aponte, Anupam Chattopadhyay. 1-6 [doi]
• Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtimeJahanzeb Anwer, Sebastian Meisner, Marco Platzner. 1-6 [doi]
• A fault attack on a hardware-based implementation of the secure hash algorithm SHA-512Abdulhadi Shoufan. 1-7 [doi]
• ReCompAc: Reconfigurable compute acceleratorMilovan Duric, Oscar Palomar, Aaron Smith. 1-4 [doi]
• An efficient application-specific instruction-set processor for packet classificationOmar Ahmed, Shawki Areibi. 1-6 [doi]
• Energy-efficient Median filter on FPGAAndrea Sanny, Viktor K. Prasanna. 1-8 [doi]
• Keynote 1 - Moore's law, programmable logic and reconfigurable systemsSteve Trimberger. 1 [doi]
• FPGA-based reconfigurable unit for image filtering in frequency domainLuis M. Ledesma-Carrillo, Misael Lopez-Ramirez, Ana L. Martinez-Herrera. 1-6 [doi]
• MCMA: A modular processing elements array based low-power coarse-grained reconfigurable acceleratorRemi Chaintreuil, Rie Uno, Hideharu Amano. 1-6 [doi]
• A robust and low resource FPGA-based stereoscopic vision algorithmS. Ibarra-Delgado, Manuel Hernandez Calviño, N. Guil Mata, Juan Gómez-Luna. 1-6 [doi]