Abstract is missing.
- A Coarse-Grain Reconfigurable Machine with Floating-Point Arithmetic CapabilitiesClaudio Brunelli, Fabio Garzia, Jari Nurmi. 1-7
- Data Transfer Protocols for a Two Slot Based Reconfigurable PlatformAlexander Warkentin, Florian Dittmann. 8-15
- A Reconfigurable Multi-Processor Platform for Convolutional and Turbo DecodingTimo Vogt, Christian Neeb, Norbert Wehn. 16-23
- MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash SituationAlain Greiner, Frédéric Pétrot, M. Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, Raphaël Labayrade. 24-30
- A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture TemplateDmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich. 31-37
- Compilation Techniques for Configurable ArchitecturesAlberto Gallini, Alberto Rosti, Sara Bocchio. 38-45
- Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained ArchitecturesCarlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein. 46-51
- How to Secure Embedded Programmable Gate Arrays?Nicolas Valette, Lionel Torres, Gilles Sassatelli, S. Bancel. 52-59
- Secure Architecture in Embedded Systems: an OverviewRomain Vaslin, Guy Gogniat, Jean-Philippe Diguet. 60-67
- Efficient Combination of Data Encryption and Integrity Checking for Embedded SystemsReouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez. 69-75
- Mixed Gates: Leakage Reduction techniques applied to Switches for Networks-on-ChipFrank Sill, Claas Cornelius, Stephan Kubisch, Dirk Timmermann. 76-82
- Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA DesignEric Senn, Nathalie Julien, David Elléouet, Yannig Savary, Nabil Abdelli. 83-90
- Partial Reconfiguration for Core Reallocation and Flexible CommunicationsYana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo. 91-97
- Clear Stream towards Dynamically Reconfigurable Systems on ChipNicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny. 98-104
- A Concept for a Profile-based Dynamic Reconfiguration MechanismHeiko Hinkelmann, Peter Zipf, Manfred Glesner. 105-110
- Resource Management for Dynamic Reconfigurable Hardware StructuresAndreas Kühn, Felix Madlener, Sorin A. Huss. 111-116
- Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection StructureHayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot. 117-123
- Remanent SRAM Structure for Runtime Reconfigurable FPGANicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon. 124-130
- Towards a SystemC TLM based Methodology for Platform Design and IP Reuse: Application to Software Defined RadioGrégory Gailliard, Bertrand Mercier, Michel Sarlotte, Bernard Candaele, François Verdier. 131-138
- An approach to Co-design of Complex Adaptive SystemsC. A. DeJuan-Esteban, Alfredo Rosado Muñoz, Emilio Soria-Olivas, M. Bataller-Mompeán, Juan Guerrero-Martínez. 139-145
- Work in Progress: FPGA Based Emulation EnvironmentGert Jervan, Anton Arhipov, Peeter Ellervee. 146-151
- Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo DecodingErwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel. 152-159
- Exploring Functional Unit Parallelism in Reconfigurable Computing PlatformsHua Zhong, Leandro Soares Indrusiak, Heiko Hinkelmann, Manfred Glesner. 160-167
- Control Unit for Parallel Embedded SystemStéphane Chevobbe, Raphaël David, Frédéric Blanc, Thierry Collette, Olivier Sentieys. 168-176
- Design of a 10000 Frames/s CMOS Sensor with In Situ Image ProcessingJerome Dubois, Dominique Ginhac, Michel Paindavoine. 177-182
- Adaptable Image Processing System based on FPGA Modular Multi Kernel InstantiationsKurt Franz Ackermann, Friedhelm Mayer, Leandro Soares Indrusiak, Manfred Glesner. 183-188
- SystemC design of a smart cameraBarthélémy Heyrman, Michel Paindavoine. 189-193
- A Comparison between NoC and Bus Architectures Based on a Real-ApplicationDiego Puschini, Fabien Clermidy. 194-200
- Embedded System Prototyping Experience Using Multi-DSPs VHDL ModelVincent Brost, Fan Yang, Michel Paindavoine. 201-206
- A Low Speed Digital Correlator Architecture Optimized For Resource SavingsJehangir Khan, Yassin Elhillali, Smaïl Niar, Atika Rivenq. 207-213
- Integrated Evaluation Platform for Secured DevicesPascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Assia Tria, Bruno Robisson, Jerome Quartana, Selma Laabidi. 214-219
- A Parallel and Secure Architecture for Asymmetric CryptographyBenoît Badrignans, Daniel Mesquita, Jean-Claude Bajard, Lionel Torres, Gilles Sassatelli, Michel Robert. 220-224
- FPGA Implementation of a Digital Jitter Measurement Method for SDH Data StreamsJan Borgosz. 225-231
- Power Macromodeling for High Level Power EstimationYaseer A. Durrani, Teresa Riesgo. 232-236
- A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication ApplicationsEtienne Faure, Alain Greiner, Daniela Genius. 237-242
- Flexible security and its technology limitsViktor Fischer, Lionel Torres, Daniel Mesquita. 243-248