Table of Contents

• Fast prototyping environment for embedded reconfigurable unitsDamien Picard, Loïc Lagadec. 1-8 [doi]
• A new mechanism to reduce congestion on TDM networks-on-chipsDaniel Vergeylen, Angelo Kuti Lusala, Jean-Didier Legat. 1-8 [doi]
• Self-reparable system on FPGA for single event upset recoveryUros Legat, Anton Biasizzo, Franc Novak. 1-6 [doi]
• Exploration of MPSoC monitoring and management systemsMohammad Fattah, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila. 1-3 [doi]
• A reconfigurable fabric supporting full C/C++ inputAlexandre A. Junqueira, Mateus B. Rutzig, Fábio P. Itturriet, João Victor Portal, Luigi Carro. 1-6 [doi]
• Extending Java for heterogeneous embedded system descriptionGary Plumbridge, Neil C. Audsley. 1-6 [doi]
• Genetic mapping of hard real-time applications onto NoC-based MPSoCs - A first approachParis Mesidis, Leandro Soares Indrusiak. 1-6 [doi]
• Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systemsFaizal Arya Samman, Surapong Pongyupinpanich, Manfred Glesner. 1-6 [doi]
• High-performance on-chip network platform for memory-on-processor architecturesMasoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 1-6 [doi]
• FPGA bitstream protection with PUFs, obfuscation, and multi-bootSezer Gören, Ozgur Ozkurt, Abdullah Yildiz, H. Fatih Ugurdag. 1-2 [doi]
• A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAsSalih Bayar, Mehmet Tükel, Arda Yurdakul. 1-9 [doi]
• Multi-objective mapping for matrix-based nanocomputer architecturesNataliya Yakymets, Sébastien Le Beux, Kotb Jabeur, Ian O'Connor. 1-7 [doi]
• A prototyping environment for high performance reconfigurable computingGeorge Afonso, Rabie Ben Atitallah, Alexander Loyer, Jean-Luc Dekeyser, Nicolas Bélanger, Martial Rubio. 1-8 [doi]
• A dependable and dynamic network on chip suitable for FPGA-based reconfigurable systemsCedric Killian, Camel Tanougast, Abbas Dandache, Mohamed Frihi, Salah Toumi. 1-6 [doi]
• Efficient congestion-aware selection method for on-chip networksMasoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 1-4 [doi]
• 2DA: Reliable and reconfigurable dynamic architectureHung-Manh Pham, Ludovic Devaux, Sébastien Pillement. 1-6 [doi]
• Simulations of NoC topologies for generalized hierarchical completely-connected networksToshinori Takabatake. 1-5 [doi]
• The co-simulation interface SystemC/Matlab applied in JPEG algorithmWalid Hassairi, Moncef Bousselmi, Mohamed Abid. 1-6 [doi]
• FPGA physical-design automation using Model-Driven EngineeringCiprian Teodorov, Damien Picard, Loïc Lagadec. 1-6 [doi]
• Monitoring communication channels on a shared memory multi-processor system on chipDaniela Genius, Nicolas Pouillon. 1-8 [doi]
• Comparison of periodic and aperiodic task models for cyber-physical-systemsAndreas Thuy. 1-2 [doi]
• Dataflow programming model for reconfigurable computingLaurent Gantel, Amel Khiar, Benoit Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, Lounis Kessal. 1-8 [doi]
• Study and modeling of a new configuration of an optical network on chip (ONOC) using FDTDMalèk Channoufi, Pierre Lecoy, Rabah Attia, Bruno Delacressonniere. 1-2 [doi]
• Achieving hardware security for reconfigurable systems on chip by a proof-carrying code approachStephanie Drzevitzky, Marco Platzner. 1-8 [doi]
• Secure remote reconfiguration of an FPGA-based embedded systemAn Braeken, Jan Genoe, Serge Kubera, Nele Mentens, Abdellah Touhafi, Ingrid Verbauwhede, Yannick Verbelen, Jo Vliegen, Karel Wouters. 1-6 [doi]
• Temperature-based covert channel in FPGA systemsTaras Iakymchuk, Maciej Nikodem, Krzysztof Kepa. 1-7 [doi]
• Self-organization of reconfigurable processing elements during mobile robots missionsLaurent Rodriguez, Jérôme Fellus, Benoit Miramond. 1-2 [doi]
• An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levelsMatthias Kühnle, Alisson Vasconcelos De Brito, Christoph Roth, Matthias Krüsselin, Jürgen Becker. 1-8 [doi]
• Partial reconfiguration in the implementation of autonomous radio receivers for spaceGian-Carlo Cardarilli, Marco Re, Ilir Shuli, Lorenzo Simone. 1-6 [doi]
• Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approachCristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Ettore Speziale, Diego Melpignano, J. M. Zins, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Junaid Ansari, Petri Mähönen, Bart Vanthournout. 1-7 [doi]
• Implementation, integration, and verification of MIMAX WLAN modemZoran Stamenkovic, Klaus Tittelbach-Helmrich, Michael Wickert, Jesús Ibáñez, Susana Ruiz, George Dimosthenous. 1-8 [doi]
• Invited paper: Design criteria for dependable System-on-Chip architecturesThomas Hollstein, Faizal Arya Samman, Ashok Jaiswal, Haoyuan Ying, Manfred Glesner, Klaus Hofmann. 1-6 [doi]
• Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and researchRené Cumplido, Claudia Feregrino Uribe, Jose Juan Garcia Hernandez. 1-6 [doi]
• SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applicationsKostas Siozios, Dionysios Diamantopoulos, Ioannis Kostavelis, Evangelos Boukas, Lazaros Nalpantidis, Dimitrios Soudris, Antonios Gasteratos, Marcos Avilés, Iraklis Anagnostopoulos. 1-9 [doi]
• Runtime-datapath-remapping for fault-tolerant coarse-grained reconfigurable architecturesSven Eisenhardt, Anja Küster, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel. 1-2 [doi]
• Towards a power and energy efficient use of partial dynamic reconfigurationRobin Bonamy, Daniel Chillet, Olivier Sentieys, Sebastien Bilavarn. 1-4 [doi]
• Invited paper: System-wide fault management based on IEEE P1687 IJTAGArtur Jutman, Sergei Devadze, Igor Aleksejev. 1-4 [doi]
• NoCmodel: An extensible framework for Network-on-Chips modelingOscar Daniel Diaz, Armando Astarloa, Aitzol Zuloaga, Jesús Lázaro, Jaime Jimenez. 1-6 [doi]
• A study on fine granular fault tolerance methodologies for FPGAsMahtab Niknahad, Oliver Sander, Jürgen Becker. 1-5 [doi]
• RecoNoC: A reconfigurable network-on-chipRobbe Vancayseele, Brahim Al Farisi, Wim Heirman, Karel Bruneel, Dirk Stroobandt. 1-2 [doi]
• Automatic saboteur placement for emulation-based multi-bit fault injectionJohannes Grinschgl, Armin Krieg, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 1-8 [doi]
• Enhancing learning of digital systems using a remote FPGA labFearghal Morgan, Seamus Cawley. 1-8 [doi]
• HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAsEduardo Wächter, Adelcio Biazi, Fernando Gehm Moraes. 1-8 [doi]
• Secure extensions of FPGA soft core processors for symmetric key cryptographyLubos Gaspar, Viktor Fischer, Lilian Bossuet, Robert Fouquet. 1-8 [doi]
• Evaluating the feasibility of network coding for NoCsLeandro Soares Indrusiak. 1-5 [doi]
• Evaluation of speculative execution techniques for high-level language to hardware compilationBenjamin Thielmann, Jens Huthmann, Andreas Koch 0001. 1-8 [doi]
• Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modelingLuciano Ost, Gabriel Marchesan Almeida, Marcelo Mandelli, Eduardo Wächter, Sameer Varyani, Gilles Sassatelli, Leandro Soares Indrusiak, Michel Robert, Fernando Moraes. 1-8 [doi]
• The Xilinx Design Language (XDL): Tutorial and use casesChristian Beckhoff, Dirk Koch, Jim Tørresen. 1-8 [doi]
• A SDM-TDM based circuit-switched router for on-chip networksAngelo Kuti Lusala, Jean-Didier Legat. 1-8 [doi]
• Approach of an FPGA based adaptive stepper motor control systemNadine Dahm, Michael Hübner, Jürgen Becker. 1-6 [doi]
• Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCsTales Marchesan Chaves, Everton Alceu Carara, Fernando Gehm Moraes. 1-6 [doi]
• Asymmetric cache coherency: Improving multicore performance for non-uniform workloadsJohn Shield, Jean-Philippe Diguet, Guy Gogniat. 1-8 [doi]
• FPGA SDK for nanoscale architecturesCiprian Teodorov, Loïc Lagadec. 1-8 [doi]
• Dynamic resource management in modern multicore SoCs by exposing NoC servicesAntonios Motakis, George Kornaros, Marcello Coppola. 1-7 [doi]
• Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGAEmna Amouri, Zied Marrakchi, Habib Mehrez. 1-4 [doi]