Abstract is missing.
- Towards Formal Verification on the System LevelRolf Drechsler. 2-5 [doi]
- Formal Specification and Verification of Embedded System with Shared ResourcesKi-Seok Bang, Jin-Young Choi, Sung-Ho Jang. 8-14 [doi]
- Automated Hardware Synthesis from Formal Specification Using SAT SolversDavid J. Greaves. 15-20 [doi]
- ASET: A Formal Model for System Emulation and VerificationSwapan Bhattacharyya, Joydeep Bhattacharyya, Adrish Ray Chaudhuri. 21-28 [doi]
- TLCharts: Armor-plating Harel Statecharts with Temporal Logic ConditionsDoron Drusinsky, Man-tak Shing. 29-36 [doi]
- Improvement of Compiled Instruction Set Simulator by Increasing Flexibility aMoo-Kyoung Chung, Chong-Min Kyung. 38-44 [doi]
- Characterizing Power Consumption and Delay of Functional/Library Components for Hardware/Software Co-Design of Embedded SystemsAmjad Mohsen, Richard Hofmann. 45-52 [doi]
- Automatic Generation of a Simulation Compiler by a HW/SW Co-Design SystemHideaki Yanagisawa, Minoru Uehara, Hideki Mori. 53-59 [doi]
- Co-Validation Environment for Memory CardChankin Park, Seungmo Cho, Jaewook Lee, Hyungjun Park. 62-65 [doi]
- Network Interface Generation for MPSOC: From Communication Service Requirements to RTL ImplementationArnaud Grasset, Frédéric Rousseau, Ahmed Amine Jerraya. 66-69 [doi]
- Rapid Prototyping and Performance Analysis for CDMA2000M. De Nobili, R. W. Stewart, G. C. Freeland. 70-73 [doi]
- State Pruning for Test Vector Generation for a Multiprocessor Cache Coherence ProtocolYing Chen, Dennis Abts, David J. Lilja. 74-77 [doi]
- An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive MultiprocessorFerid Gharsalli, Amer Baghdadi, Marius Bonaciu, Giedrius Majauskas, Wander O. Cesário, Ahmed Amine Jerraya. 80-87 [doi]
- Automatic Building of Executable Models from Abstract SoC Architectures Made of Heterogeneous SubsystemsAdriano Sarmento, Wander O. Cesário, Ahmed Amine Jerraya. 88-95 [doi]
- Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping BoardsRawat Siripokarpirom, Friedrich Mayer-Lindenberg. 96-102 [doi]
- High Level Synthesis Methodology from C to FPGA Used for a Network Protocol CommunicationM. Diaby, Matthieu Tuna, Jean Lou Desbarbieux, Franck Wajsbürt. 103-108 [doi]
- Domain Driven Software Development -- A World of TransformationsShane Sendall. 110-112 [doi]
- Automatic Generation of Virtual PrototypesPavle Belanovic, Martin Holzer 0002, Bastian Knerr, Markus Rupp, Guillaume Sauzon. 114-118 [doi]
- Rapid Software Prototyping Using Visual Language TechniquesKang Zhang, Guang-Lei Song, Jun Kong. 119-126 [doi]
- Generation of Distributed Programs in Their Target Execution EnvironmentFrédéric Gilliers, Jean-Pierre Velu, Fabrice Kordon. 127-134 [doi]
- Approaching Interoperability from the Bottom up: A Lattice Structure for the Object-Oriented Method for Interoperability (OOMI)George M. Lawler, Paul E. Young. 135-142 [doi]
- Self-Reconfiguration of Communication InterfacesAndré Meisel, Markus Visarius, Wolfram Hardt, Stefan Ihmor. 144-150 [doi]
- Multi-User FPGA Co-Simulation over TCP/IPDaniel Denning, James Irvine, Derek Stark, Malachy Devlin. 151-156 [doi]
- SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA ImplementationCamel Tanougast, Yves Berviller, Christian Mannino, Hassan Rabah, Michael Janiaut, Serge Weber. 157-163 [doi]
- Rapid Prototyping of a Co-Designed Java Virtual MachineKenneth B. Kent, Hejun Ma, Micaela Serra. 164-171 [doi]
- Transmission Systems Prototyping Based on Stateflow/Simulink ModelsNikolaos Papandreou, Maria Varsamou, Theodore Antonakopoulos. 174-179 [doi]
- A Case Study on Rapid Prototyping of Hardware Systems: The Effect of CAD Tool Capabilities, Design Flows, and Design StylesApostolos Dollas, Kyprianos Papademetriou, Euripides Sotiriades, Dimitrios Theodoropoulos, Iosif Koidis, George Vernardos. 180-186 [doi]
- Rapid Prototyping of an Integrated Testing and Debugging UnitRalf Ludewig, Thomas Hollstein, Falko Schütz, Manfred Glesner. 187-192 [doi]
- Transaction-Level Prototyping of a UMTS Outer-Modem for System-on-Chip Validation and Architecture ExplorationPaolo Martinelli, Armin Wellig, Julien Zory. 193-200 [doi]
- Modeling and Simulation of System-of-Systems Timing Constraints with UML-RT and OMNeT++James Bret Michael, Man-tak Shing, Michael H. Miklaski, Joel D. Babbitt. 202-209 [doi]
- Abstract RTOS Modeling for Embedded SystemsFabiano Hessel, Vitor M. da Rosa, Igor M. Reis, Ricardo Planner, César A. M. Marcon, Altamiro Amadeu Susin. 210-216 [doi]
- Architecture Exploration of a Large Scale SystemSylvain Alliot, Ed F. Deprettere. 217-224 [doi]
- Real Time Prototyping of Broadband Wireless LAN SystemsMaryse Wouters, Peter Van Wesemael, Roeland Vandebriel, Andy Dewilde, Michael Libois. 226-231 [doi]
- Implementation of a Channel Equalizer for OFDM Wireless LANsMoisès Serra, Pere Martí, Jordi Carrabina. 232-238 [doi]
- Prototyping with a Bio-Inspired Reconfigurable ChipYann Thoma, Eduardo Sanchez, Daniel Roggen, Carl Hetherington, Juan Manuel Moreno. 239-246 [doi]