Abstract is missing.
- Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-PassAndre Silva, Guilherme Esmeraldo, Edna Barros, Pablo Viana. 3-9 [doi]
- Codesign of a Computationally Intensive Problem in GF(3)Kenneth B. Kent, Beatriz C. Iaderoza, Micaela Serra. 10-16 [doi]
- Unified Inter-Communication Architecture for Systems-on-ChipFernando Rincón, Jesús Barba, Francisco Moya, Felix Jesús Villanueva, David Villa, Julio Dondo, Juan Carlos López. 17-26 [doi]
- SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection SystemsLuis Carlos Caruso, Guilherme Guindani, Hugo Schmitt, Ney Calazans, Fernando Moraes. 27-33 [doi]
- Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCsEwerson Carvalho, Ney Calazans, Fernando Moraes. 34-40 [doi]
- Hardware Implementation of 2-Opt Local Search Algorithm for the Traveling Salesman ProblemIoannis Mavroidis, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos. 41-47 [doi]
- Hardware/Firmware Verification of Graphic IPRomain Kamdem. 48-56 [doi]
- Communication Models in Networks-on-ChipEverton Carara, Aline Mello, Fernando Moraes. 57-60 [doi]
- A Lightweight Framework for Runtime Reconfigurable System PrototypingRoman Koch, Thilo Pionteck, Carsten Albrecht, Erik Maehle. 61-64 [doi]
- Design and Implementation of a Reconfigurable, Embedded Real-Time Face Detection SystemV. Mariatos, K. Adaos, George Alexiou. 65-68 [doi]
- Object-Oriented ReconfigurationJúlio C. B. de Mattos, Antonio Carlos Schneider Beck, Luigi Carro. 69-74 [doi]
- A Semantics for UML-RT using n-calculusJuliana de Melo Bezerra, Celso Massaki Hirata. 75-82 [doi]
- Verifying Distributed Protocols using MSC-Assertions, Run-time Monitoring, and Automatic Test GenerationDoron Drusinsky, Man-tak Shing. 82-88 [doi]
- Rapid Prototyping of Intrusion Detection SystemsFabrice Kordon, Jean-Baptiste Voron. 89-98 [doi]
- A Tailored Design Partitioning Method for Hardware EmulationRene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt. 99-105 [doi]
- Rapid Prototyping of Distributed Real-Time Embedded Systems Using the AADL and OcarinaJérôme Hugues, Bechir Zalila, Laurent Pautet, Fabrice Kordon. 106-112 [doi]
- Efficient Software Development Platforms for Multimedia Applications at Different Abstraction LevelsKatalin Popovici, Xavier Guerin, Frédéric Rousseau, Pier Stanislao Paolucci, Ahmed Amine Jerraya. 113-122 [doi]
- A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and EvaluationFernando Kronbauer, Alexandro Baldassin, Bruno Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo. 123-129 [doi]
- Nonintrusive Black- and White-Box Testing of Embedded Systems Software against UML ModelsPhilipp Graf, Klaus D. Müller-Glaser, Clemens Reichmann. 130-138 [doi]
- Architectural Issues in Homogeneous NoC-Based MPSoCGilles Sassatelli, Nicolas Saint-Jean, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes. 139-142 [doi]
- Using Synchronizers for Refining Synchronous Communication onto Hardware/Software ArchitecturesZhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch. 143-149 [doi]
- Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency SynthesizersHimanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick Wolf. 150-156 [doi]
- Behavioral synthesis of property specification language (PSL) assertionsHarald Obereder, Markus Pfaff. 157-160 [doi]
- Structured Approach to Property Specification and Verification of HW IPLyes Benalycherif, Anthony McIsaac, Neil Dunlop. 161-166 [doi]
- A CABAC Encoder Design of H.264/AVC with RDO SupportX. H. Tian, Thinh M. Le, B. L. Ho, Yong Lian. 167-173 [doi]
- FPGA Prototyping Strategy for a H.264/AVC Video DecoderVagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin. 174-180 [doi]
- ER-EDF: A QoS Scheduler for Real-Time Embedded SystemsDavid Matschulat, César A. M. Marcon, Fabiano Hessel. 181-188 [doi]
- Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW ProcessorsAnupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 189-194 [doi]
- Low Runtime-Overhead Software Synthesis for Communicating Concurrent ProcessesYoungchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya. 195-201 [doi]
- A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based ApplicationsChanik Park, Wonmoon Cheon, Yangsup Lee, Myoung-Soo Jung, Wonhee Cho, Hanbin Yoon. 202-208 [doi]