Abstract is missing.
- Message from the Program and Track ChairsRichard West, James H. Anderson, Samarjit Chakraborty. [doi]
- The Multi-Resource Server for predictable execution on multi-core platformsRafia Inam, Nesredin Mahmud, Moris Behnam, Thomas Nolte, Mikael Sjödin. 1-12 [doi]
- Towards certifiable adaptive reservations for hypervisor-based virtualizationStefan Groesbrink, Luis Almeida, Mario de Sousa, Stefan M. Petters. 13-24 [doi]
- FJOS: Practical, predictable, and efficient system support for fork/join parallelismQi Wang, Gabriel Parmer. 25-36 [doi]
- SAFER SLOTH: Efficient, hardware-tailored memory protectionDaniel Danner, Rainer Muller, Wolfgang Schröder-Preikschat, Wanja Hofer, Daniel Lohmann. 37-48 [doi]
- Schedulability tests for tasks with Variable Rate-dependent Behaviour under fixed priority schedulingRobert I. Davis, Timo Feld, Victor Pollex, Frank Slomka. 51-62 [doi]
- Real-time scheduling under fault bursts with multiple recovery strategyMohammad A. Haque, Hakan Aydin, Dakai Zhu. 63-74 [doi]
- Hiding memory latency using fixed priority schedulingSaud Wasly, Rodolfo Pellizzoni. 75-86 [doi]
- Relaxing the synchronous approach for mixed-criticality systemsEugene Yip, Matthew M. Y. Kuo, Partha S. Roop, David Broman. 89-100 [doi]
- FlexPRET: A processor platform for mixed-criticality systemsMichael Zimmer, David Broman, Chris Shaver, Edward A. Lee. 101-110 [doi]
- Partitioned scheduling of multi-modal mixed-criticality real-time systems on multiprocessor platformsDionisio de Niz, Linh T. X. Phan. 111-122 [doi]
- Precise shared cache analysis using optimal interference placementKartik Nagar, Y. N. Srikant. 125-134 [doi]
- Selfish-LRU: Preemption-aware caching for predictability and performanceJan Reineke, Sebastian Altmeyer, Daniel Grund, Sebastian Hahn 0001, Claire Maiza. 135-144 [doi]
- Bounding memory interference delay in COTS-based multi-core systemsHyoseung Kim, Dionisio de Niz, Björn Andersson, Mark H. Klein, Onur Mutlu, Ragunathan Rajkumar. 145-154 [doi]
- PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platformsHeechul Yun, Renato Mancuso, Zheng Pei Wu, Rodolfo Pellizzoni. 155-166 [doi]
- Trickle: Automated infeasible path detection using all minimal unsatisfiable subsetsBernard Blackham, Mark H. Liffiton, Gernot Heiser. 169-178 [doi]
- WCET-aware dynamic code management on scratchpads for Software-Managed MulticoresYooseong Kim, David Broman, Jian Cai, Aviral Shrivastava. 179-188 [doi]
- Architecture-parametric timing analysisJan Reineke, Johannes Doerfert. 189-200 [doi]
- Slack-aware opportunistic monitoring for real-time systemsDaniel Lo, Mohamed Ismail, Tao Chen, G. Edward Suh. 203-214 [doi]
- A network virtualization approach for performance isolation in controller area network (CAN)Christian Herber, Andre Richter, Thomas Wild, Andreas Herkersdorf. 215-224 [doi]
- AHRB: A high-performance time-composable AMBA AHB busJavier Jalle, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla. 225-236 [doi]
- MAESTRO: A time-driven embedded testbed Architecture with Event-driven SynchronizationSriram Karunagaran, Karuna P. Sahoo, Jayaraj Poroor, Masahiro Fujita. 237-248 [doi]
- Overhead-aware temporal partitioning on multicore processorsRisat Mahmud Pathan, Per Stenström, Lars-Goran Green, Torbjorn Hult, Patrik Sandin. 251-262 [doi]
- Scaling global scheduling with message passingFelipe Cerqueira, Manohar Vanga, Böorn B. Brandenburg. 263-274 [doi]
- Has energy surpassed timeliness? Scheduling energy-constrained mixed-criticality systemsMarcus Völp, Marcus Hähnel, Adam Lackorzynski. 275-284 [doi]
- Unifying DVFS and offlining in mobile multicoresAaron Carroll, Gernot Heiser. 287-296 [doi]
- STCoS: Software-defined traffic control for smartphonesYoshikazu Watanabe, Shuichi Karino, Yoshinori Saida, Gen Morita, Takahiro Iihoshi. 297-308 [doi]
- The ROSACE case study: From Simulink specification to multi/many-core executionClaire Pagetti, David Saussié, Romain Gratia, Eric Noulard, Pierre Siron. 309-318 [doi]