Abstract is missing.
- What Else Is Broken? Can We Fix It?Yale N. Patt. 1 [doi]
- Programmable and Scalable Architecture for Graphics Processing UnitsCarlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala. 2-11 [doi]
- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous MultiprocessorsPaul M. Carpenter, Alex RamÃrez, Eduard Ayguadé. 12-23 [doi]
- CABAC Accelerator Architectures for Video Compression in Future Multimedia: A SurveyYahya Jan, Lech Józwiak. 24-35 [doi]
- Programmable Accelerators for Reconfigurable Video DecoderTero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silvén. 36-47 [doi]
- Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case StudyNarasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor. 48-57 [doi]
- Multiple Description Scalable Coding for Video Transmission over Unreliable NetworksRoya Choupani, Stephan Wong, Mehmet R. Tolun. 58-67 [doi]
- Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPCSascha Uhrig. 68-77 [doi]
- Implementing Fine/Medium Grained TLP Support in a Many-Core ArchitectureRoberto Giorgi, Zdravko Popovic, Nikola Puzovic. 78-87 [doi]
- Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power ManagementRoberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi. 88-97 [doi]
- A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCAChristian Schäck, Wolfgang Heenes, Rolf Hoffmann. 98-107 [doi]
- Towards Automated FSMD Partitioning for Low Power Using Simulated AnnealingNainesh Agarwal, Nikitas J. Dimopoulos. 108-117 [doi]
- Radix-4 Recoded Multiplier on Quantum-Dot Cellular AutomataIsmo Hänninen, Jarmo Takala. 118-127 [doi]
- Prediction in Dynamic SDRAM Controller PoliciesYing Xu, Aabhas S. Agarwal, Brian T. Davis. 128-138 [doi]
- Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSIShinichi Kato, Minoru Watanabe. 139-148 [doi]
- Visualization of Computer Architecture Simulation Data for System-Level Design Space ExplorationToktam Taghavi, Mark Thompson, Andy D. Pimentel. 149-160 [doi]
- Modeling Scalable SIMD DSPs in LISAPeter Westermann, Hartmut Schröder. 161-170 [doi]
- NoGAP: A Micro Architecture Construction FrameworkPer Karlström, Dake Liu. 171-180 [doi]
- A Comparison of NoTA and GENESYSBernhard Huber, Roman Obermaisser. 181-192 [doi]
- Introduction to Instruction-Set CustomizationCarlo Galuzzi. 193 [doi]
- Constraint-Driven Identification of Application Specific Instructions in the ::::DURASE:::: SystemKevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot. 194-203 [doi]
- A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 204-214 [doi]
- Runtime Adaptive Extensible Embedded Processors - A SurveyHuynh Phung Huynh, Tulika Mitra. 215-225 [doi]
- Introduction to the Future of Reconfigurable Computing and Processor ArchitecturesLuigi Carro, Stephan Wong. 226 [doi]
- An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous SystemsRainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl. 227-236 [doi]
- Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case StudyFrederico Pratas, Leonel Sousa. 237-246 [doi]
- Reconfigurable Multicore Server Processors for Low Power OperationRonald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor N. Mudge. 247-254 [doi]
- Reconfigurable Computing in the New Age of ParallelismWalid A. Najjar, Jason R. Villarreal. 255-262 [doi]
- Reconfigurable Multithreading Architectures: A SurveyPavel G. Zaykov, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev. 263-274 [doi]
- Introduction to Mastering Cell BE and GPU Execution PlatformsEd F. Deprettere, Ana Lucia Varbanescu. 275-276 [doi]
- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics ProcessorsRichard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich. 277-288 [doi]
- Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUsAlexander Monakov, Arutyun Avetisyan. 289-297 [doi]
- Experiences with Cell-BE and GPU for TomographySander van der Maar, Kees Joost Batenburg, Jan Sijbers. 298-307 [doi]
- Realizing FIFO Communication When Mapping Kahn Process Networks onto the CellDmitry Nadezhkin, Sjoerd Meijer, Todor Stefanov, Ed F. Deprettere. 308-317 [doi]
- Exploiting Locality on the Cell/B.E. through BypassingPieter Bellens, Josep M. Pérez, Rosa M. Badia, Jesús Labarta. 318-328 [doi]
- Exploiting the Cell/BE Architecture with the StarPU Unified Runtime SystemCédric Augonnet, Samuel Thibault, Raymond Namyst, Maik Nijhuis. 329-339 [doi]