Abstract is missing.
- Mobile visual computingKari Pulli. [doi]
- Slower than you think - The evolution of processor and SoC architecturesGrant Martin. [doi]
- A mixed hardware-software approach to flexible Artificial Neural Network training on FPGARamón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá, Néstor Ferrando, Vicente Herrero. 1-8 [doi]
- High-speed FPGA-based implementations of a Genetic AlgorithmMichalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou. 9-16 [doi]
- OpenMP extensions for FPGA acceleratorsDaniel Cabrera, Xavier Martorell, Georgi Gaydadjiev, Eduard Ayguadé, Daniel Jiménez-González. 17-24 [doi]
- High-level synthesis for the design of FPGA-based signal processing systemsEmmanuel Casseau, Bertrand Le Gal. 25-32 [doi]
- Instruction scheduling for VLIW processors under variation scenarioNayan V. Mujadiya. 33-40 [doi]
- A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processorsElham Safi, Andreas Moshovos, Andreas G. Veneris. 41-48 [doi]
- Instruction-based reuse-distance prediction for effective cache managementPavlos Petoumenos, Georgios Keramidas, Stefanos Kaxiras. 49-58 [doi]
- Adaptive simulation sampling using an Autoregressive frameworkSharookh Daruwalla, Resit Sendag, Joshua J. Yi. 59-66 [doi]
- An emulation-based real-time power profiling unit for embedded softwareAndreas Genser, Christian Bachmann, Josef Haid, Christian Steger, Reinhold Weiss. 67-73 [doi]
- A timed HW/SW coemulation technique for fast yet accurate system verificationHoeseok Yang, Youngmin Yi, Soonhoi Ha. 74-81 [doi]
- RETHROTTLE: Execution throttling in the REDEFINE SoC architectureA. N. Satrawala, S. K. Nandy. 82-91 [doi]
- Generation and calibration of compositional performance analysis models for multi-processor systemsWolfgang Haid, Matthias Keller, Kai Huang, Iuliana Bacivarov, Lothar Thiele. 92-99 [doi]
- Performance evaluation of concurrently executing parallel applications on multi-processor systemsAhsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal. 100-107 [doi]
- Manycore performance analysis using timed configuration graphsJerker Bengtsson, Bertil Svensson. 108-117 [doi]
- Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniquesGiovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. 118-124 [doi]
- Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architecturesHolger Flatt, Ingo Schmadecke, Mmichael Kärgel, Holger Blume, Peter Pirsch. 125-132 [doi]
- Synchronization on heterogeneous multiprocessor systemsMayan Moudgill, Vitaly Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Tak-po Li, Pablo I. Balzola, John Glossner. 133-139 [doi]
- Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphsTjerk Bijlsma, Marco Bekooij, Gerard J. M. Smit. 140-148 [doi]
- FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capabilityGeorge Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Manolis Katevenis, Dionisios N. Pnevmatikatos, Xiaojun Yang. 149-156 [doi]
- High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architecturesGanesh Garga, David Guevorkian, S. K. Nandy, H. S. Jamadagni. 157-164 [doi]
- Novel energy-efficient scalable soft-output SSFE MIMO detector architecturesRobert Fasthuber, Min Li, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor. 165-171 [doi]
- Customizing wide-SIMD architectures for H.264Sangwon Seo, Mark Woh, Scott A. Mahlke, Trevor N. Mudge, Sunfaram Vijay, Chaitali Chakrabarti. 172-179 [doi]
- Parallel implementation of convolution encoder for software defined radio on DSP architectureJui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen, Yu Hen Hu. 180-186 [doi]