Table of Contents

• Technologies for reducing powerTrevor N. Mudge. [doi]
• Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulatorIgor Böhm, Björn Franke, Nigel P. Topham. 1-10 [doi]
• A trace-based scenario database for high-level simulation of multimedia MP-SoCsPeter van Stralen, Andy D. Pimentel. 11-19 [doi]
• A library of dual-clock FIFOs for cost-effective and flexible MPSoC designAlessandro Strano, Daniele Ludovici, Davide Bertozzi. 20-27 [doi]
• Transparent samplingTaj Muhammad Khan, Daniel Gracia Pérez, Olivier Temam. 28-36 [doi]
• Design of a flexible high-speed FPGA-based flow monitor for next generation networksJohn McGlone, Roger Woods, Alan J. Marshall, Michaela Blott. 37-44 [doi]
• A fully programmable FSM-based Processing Engine for Gigabytes/s header parsingKonstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer. 45-54 [doi]
• Empirical evaluation of data transformations for network infrastructure applicationsDamon Fenacci, Björn Franke. 55-62 [doi]
• Design environment for the support of configurable Network Interfaces in NoC-based platformsAmin El Mrabti, Frédéric Rousseau, Frédéric Pétrot, Jérôme Martin, Romain Lemaire, Emmanuel Vaumorin. 63-70 [doi]
• An efficient realization of forward integer transform in H.264/AVC intra-frame encoderMuhammad Nadeem, Stephan Wong, Georgi Kuzmanov. 71-78 [doi]
• SIMD performance in software based mobile video codingTero Rintaluoma, Olli Silvén. 79-85 [doi]
• Fast Huffman decoding by exploiting data level parallelismTim Drijvers, Carlos A. Alba Pinto, Henk Corporaal, Bart Mesman, Gert-Jan van den Braak. 86-92 [doi]
• Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementationChristian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch. 93-101 [doi]
• Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platformsSotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Z. Pekmestzi. 102-109 [doi]
• Power aware heterogeneous MPSoC with dynamic task scheduling and increased data locality for multiple applicationsOliver Arnold, Gerhard Fettweis. 110-117 [doi]
• A system-level synthesis approach from formal application models to generic bus-based MPSoCsJens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich. 118-125 [doi]
• ImpBench revisited: An extended characterization of implant-processor benchmarksChristos Strydis, Dhara Dave, Georgi Gaydadjiev. 126-135 [doi]
• Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphsHojin Kee, Shuvra S. Bhattacharyya, Jacob Kornerup. 136-143 [doi]
• Compositional timing analysisAmine Marref. 144-151 [doi]
• Programming multi-core architectures using Data-Flow techniquesSamer Arandi, Paraskevas Evripidou. 152-161 [doi]
• CLI-based compilation flows for the C languageErven Rohou, Andrea C. Ornstein, Marco Cornero. 162-169 [doi]
• Design space exploration of instruction set customizable MPSoCs for multimedia applicationsUnmesh D. Bordoloi, Huynh Phung Huynh, Tulika Mitra, Samarjit Chakraborty. 170-177 [doi]
• Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architectureN. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan. 178-184 [doi]
• On-chip network interfaces supporting automatic burst write creation, posted writes and read prefetchRadu Stefan, Jason de Windt, Kees G. W. Goossens. 185-192 [doi]
• Monitor-adapter coupling for NOC performance tuningDebora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Márcio Eduardo Kreutz. 193-199 [doi]
• Compile-time GPU memory access optimizationsGert-Jan van den Braak, Bart Mesman, Henk Corporaal. 200-207 [doi]
• Code generation for a novel STA architecture by using post-processing backendXiaoyan Jia, Gerhard Fettweis. 208-215 [doi]
• Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware acceleratorsJens Huthmann, Peter Muller, Florian Stock, Dietmar Hildenbrand, Andreas Koch. 216-222 [doi]
• OpenCL-based design methodology for application-specific processorsPekka O. Jaskelainen, Carlos S. de La Lama, Pablo Huerta, Jarmo Takala. 223-230 [doi]
• LV:::*:::: A low complexity lazy versioning HTM infrastructureAnurag Negi, M. M. Waliullah, Per Stenström. 231-240 [doi]
• A Polymorphic Register File for matrix operationsCatalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev, Alex Ramírez. 241-249 [doi]
• Interleaving granularity on high bandwidth memory architecture for CMPsFelipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramírez. 250-257 [doi]
• Automatic port and bus sizing in NoGapPer Karlström, Wenbiao Zhou, Dake Liu. 258-264 [doi]
• Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platformPrasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan. 265-272 [doi]
• Energy-aware design space exploration of registerfile for extensible processorsAmir Yazdanbakhsh, Mehdi Kamal, Mostafa E. Salehi, Hamid Noori, Sied Mehdi Fakhraie. 273-281 [doi]
• Exploring the unified design-space of custom-instruction selection and resource sharingMarcela Zuluaga, Nigel P. Topham. 282-291 [doi]
• Special session on software defined radio (SDR) and Cognitive Radio (CR)John Glossner. 292 [doi]
• A GPU implementation for two MIMO-OFDM detectorsTeemu Nylanden, Janne Janhunen, Olli Silvén, Markku J. Juntti. 293-300 [doi]
• CORDIC-based LMMSE equalizer for Software Defined RadioMurugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael J. Schulte, John Glossner. 301-308 [doi]
• On the scalability of SIMD processing for software defined radio algorithmsPeter Westermann, Hartmut Schröder. 309-317 [doi]
• SDR platform for 802.11n and 3-GPP LTEJeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre. 318-323 [doi]
• ARAL-CR: An adaptive reasoning and learning cognitive radio platformSao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael J. Schulte, Yu Hen Hu. 324-331 [doi]
• Special session on multicore architectures for embedded systemsLuigi Carro, Stephan Wong. 332 [doi]
• Exploration framework for Run-time Resource Management of embedded multi-core platformsChantal Ykman-Couvreur. 333-340 [doi]
• Towards scalable I/O on a many-core architectureMichael A. Hicks, Michiel W. van Tol, Chris R. Jesshope. 341-348 [doi]
• Embedded multicore architectures for LDPC decodingGabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva. 349-356 [doi]
• Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoCDiana Göhringer, Michael Hübner, Laure Hugot-Derville, Jürgen Becker. 357-364 [doi]
• Designing and validating access policies to reconfigurable resources in Multiprocessor Systems on chipFabio Arlati, Francesco Bruschi, Donatella Sciuto. 365-371 [doi]
• Identifying communication models in Process Networks derived from Weakly Dynamic ProgramsDmitry Nadezhkin, Todor Stefanov. 372-379 [doi]