Table of Contents

• Sizing CMOS circuits by means of the gm/ID methodology and a compact modelPaul G. A. Jespers. 1 [doi]
• Synergistic modeling and optimization for nanometer IC design/manufacturing integrationDavid Z. Pan. 2 [doi]
• Test Methods For Sigma-Delta Data Converters and Related DevicesGordon W. Roberts. 3 [doi]
• Highly integrated, re-configurable RF front-ends in deep sub-micron CMOS: (with an example of a WCDMA, GSM/GPRS/EDGE receiver without inter-stage SAW filter)Naveen K. Yanduru. 4 [doi]
• System-level design technologies for heterogeneous distributed systemsGiovanni De Micheli. 5 [doi]
• Lithography friendly routing: from construct-by-correction to correct-by-constructionDavid Z. Pan. 6 [doi]
• Time-domain analog signal processing techniquesGordon W. Roberts, Mohammad Ali-Bakhshian. 7 [doi]
• System design for 3D Silicon integrationAhmed Maine Jerraya. 8 [doi]
• Challenges of the nanoscale eraRicardo P. Jacobi, Reinaldo A. Bergamaschi. 9 [doi]
• Full-chip routing system for reducing Cu CMP & ECP variationYanming Jia, Yici Cai, Xianlong Hong. 10-15 [doi]
• Metal filling impact on standard cells: definition of the metal fill corner conceptLaurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean Michel Portal. 16-21 [doi]
• A comparative analysis of fault injection methods via enhanced on-chip debug infrastructuresAndré V. Fidalgo, Gustavo R. Alves, Manuel G. Gericota, Jose M. Martins Ferreira. 22-27 [doi]
• A new march sequence to fit DDR SDRAM test in burst modeAndré Borin Soares, Alexsandro Cristovão Bonatto, Altamiro Amadeu Susin. 28-33 [doi]
• An efficient test and characterization approach for nanowire-based architecturesEduardo Luis Rhod, Luigi Carro. 34-39 [doi]
• Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGAAbner Correa Barros, Victor Wanderley Costa Medeiros, Viviane Lucy Santos Souza, Paulo Sérgio Brandão Nascimento, Ângelo Mazer, João Paulo Barbosa, Bruno P. Neves, Ismael Santos, Manoel Eusebio de Lima. 40-45 [doi]
• The performance of pollution control victim cache for embedded systemsGiancarlo C. Heck, Roberto A. Hexsel. 46-51 [doi]
• Low-area ASIC implementation for configurable coefficients FIR pulse shape filters of digital TV systemsWagner Vieira Silvério, Janaína Domingues Costa, João Leonardo Fragoso, Julio Leão Silva Jr.. 52-57 [doi]
• An approximate algorithm for the multiple constant multiplications problemLevent Aksoy, Ece Olcay Gunes. 58-63 [doi]
• Area optimization algorithms in high-speed digital FIR filter synthesisLevent Aksoy, Ece Olcay Gunes. 64-69 [doi]
• A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM modelRafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías, Diego Vázquez, Adoración Rueda, José Luis Huertas. 70-75 [doi]
• A 40mhz 70db gain variable gain amplifier design using the gm/id design methodFernando da Rocha Paixão Cortes, Sergio Bampi. 76-80 [doi]
• A 2.7ua sub1-v voltage referenceJuan Mateus, Elkim Roa, Hugo Daniel Hernández, Wilhelmus A. M. Van Noije. 81-84 [doi]
• A wide band CMOS differential voltage-controlled ring oscillatorLuciano Severino de Paula, Altamiro Amadeu Susin, Sergio Bampi. 85-89 [doi]
• RBF circuits based on folded cascode differential pairsMarcio Barbosa Lucks, Nobuo Oki. 90-93 [doi]
• A current limiter for DC/DC regulators with internal compensation for process and temperatureJader A. De Lima, Wallace A. Pimenta. 94-99 [doi]
• Current mode read-out circuit for infrared photodiode applications in 0.35 ::::mu::::m cmosPietro Maris Ferreira, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia. 100-104 [doi]
• Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistorsEduardo Conrad Jr., Fernando da Rocha Paixão Cortes, Sergio Bampi, Alessandro Girardi. 105-110 [doi]
• Encountering gate oxide breakdown with shadow transistors to increase reliabilityClaas Cornelius, Frank Sill, Hagen Sämrow, Jakob Salzmann, Dirk Timmermann, Diógenes Cecilio da Silva Jr.. 111-116 [doi]
• A novel scheme to reduce short-circuit power in mesh-based clock architecturesGustavo Wilke, Renan Fonseca, Cecilia Mezzomo, Ricardo Reis. 117-122 [doi]
• Power and performance tradeoffs with process variation resilient adaptive cache architecturesMahmoud Ben Naser, Csaba Andras Moritz. 123-128 [doi]
• Power management techniques for very low consumption and EMI reduction in automotive applicationsEduardo Ribeiro da Silva, Ivan Carlos Ribeiro do Nascimento, Frank Herman Behrens, Marcos Mauricio Pelicia, Remerson Stein Kickhofel, Ricardo Maltione. 129-133 [doi]
• A coloured petri net based approach for estimating execution time and energy consumption in embedded systemsGustavo Rau de Almeida Callou, Paulo Romero Martins Maciel, Ermeson Carneiro de Andrade, Bruno Costa e Silva Nogueira, Eduardo Antonio Guimarães Tavares. 134-139 [doi]
• A novel AES cryptographic core highly resistant to differential power analysis attacksFelipe Ghellar, Marcelo Lubaszewski. 140-145 [doi]
• An improved and automated design tool for the optimization of CMOS OTAs using geometric programmingJorge Oliveros, Dwight Cabrera, Elkim Roa, Wilhelmus A. M. Van Noije. 146-151 [doi]
• CMOS op-amp power optimization in all regions of inversion using geometric programmingPablo Aguirre, Fernando Silveira. 152-157 [doi]
• Systematic methodology for the design of Seevinck s CMOS log-domain integratorsVictor Ariel Leal Sobral, Roberto Espinheira da Costa Bomfim, Robson Nunes de Lima, Ana Isabela Araújo Cunha. 158-163 [doi]
• BenCGen: a digital circuit generation tool for benchmarksFabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes. 164-169 [doi]
• A simplified executable model to evaluate latency and throughput of networks-on-chipLuciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi. 170-175 [doi]
• Executable formal specification and validation of NoC communication infrastructuresDominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz. 176-181 [doi]
• MOTIM: an industrial application using nocsFernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans. 182-187 [doi]
• Fault-tolerance in FPGA s through CRC votingHelano Castro, Alexandre Augusto Coelho, Ricardo Jardel Silveira. 188-192 [doi]
• Evaluating the robustness of secure triple track logic through prototypingRafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert. 193-198 [doi]
• Synchronizing triple modular redundant designs in dynamic partial reconfiguration applicationsConrado Pilotto, José Rodrigo Azambuja, Fernanda Lima Kastensmidt. 199-204 [doi]
• Self-adaptable slew rate control output buffer for embedded microcontroller port applicationsAndre Vilas Boas, Eduardo Ribeiro, Alfredo Olmos, Ricardo Maltione. 205-209 [doi]
• Efficient dynamic reconfiguration for multi-context embedded FPGAJulien Lallet, Sébastien Pillement, Olivier Sentieys. 210-215 [doi]
• Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTVMarcelo Schiavon Porto, Sergio Bampi, Altamiro Amadeu Susin, Luciano Volcan Agostini. 216-221 [doi]
• A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filterRonaldo Husemann, Altamiro Amadeu Susin, Valter Roesler. 222-227 [doi]
• High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTVBruno Zatt, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini. 228-232 [doi]
• Analog hardware implementation of a vector quantizer for focal-plane image compressionHugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia. 233-238 [doi]
• A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysisDieison Antonello Deprá, Vagner Santos Da Rosa, Sergio Bampi. 239-244 [doi]