Abstract is missing.
- Adaptable wire-length distribution with tunable occupation probabilityShuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu. 1-8 [doi]
- Stochastic interconnect layout sensitivity modelPayman Zarkesh-Ha, Ken Doniger. 9-14 [doi]
- Tutorial on congestion predictionTaraneh Taghavi, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh. 15-24 [doi]
- An accurate and efficient probabilistic congestion estimation model in x architectureYaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma. 25-32 [doi]
- Congestion estimation and localization in FPGAS: a visual tool for interconnect predictionDavid Yeager, Darius Chiu, Guy G. Lemieux. 33-40 [doi]
- Principle hessian direction based parameter reduction for interconnect networks with process variationAlexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang. 41-46 [doi]
- Statistical circuit optimization considering device andinterconnect process variationsI-Jye Lin, Tsui-Yee Ling, Yao-Wen Chang. 47-54 [doi]
- Networks on chips: keeping up with Rent s rule and Moore s lawAvinoam Kolodny. 55-56 [doi]
- Early wire characterization for predictable network-on-chip global interconnectsIlhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli. 57-64 [doi]
- Synthetic traffic generation as a tool for dynamic interconnect evaluationWim Heirman, Joni Dambre, Jan Van Campenhout. 65-72 [doi]
- Impact of interconnect length changes on effective materials properties (dielectric constant)Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand. 73-80 [doi]
- Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnectsHoyeol Cho, Kyung-Hoae Koo, Pawan Kapur, Krishna Saraswat. 81-88 [doi]
- The nuts and bolts of physical synthesisCharles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz. 89-94 [doi]
- Fast dual-vdd buffering based on interconnect prediction and samplingYu Hu, King Ho Tam, Tong Jing, Lei He. 95-102 [doi]
- Exploiting on-chip data behavior for delay minimizationNallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu. 103-110 [doi]