Table of Contents

• A 120nm CMOS Fully Differential Rail-to-Rail I/O Opamp with Highly Constant Signal BehaviorWeixun Yan, Horst Zimmermann. 3-6 [doi]
• A CMOS Low-Noise, Low-Dropout Regulator for Transceiver SOC Supply ManagementWonseok Oh, Bertan Bakkaloglu, Bhaskar Aravind, Siew Kuok Hoon. 7-10 [doi]
• Energy-Aware MPEG-4 Single Profile in HW-SW Multi-Platform ImplementationAntoni Portero, Guillermo Talavera, Marius Monton, Borja Martínez, Marc Moreno, Francky Catthoor, Jordi Carrabina. 13-16 [doi]
• A Real Time Programmable Encoder for Low Density Parity Check Code as specified in the IEEE P802.16E/D7 Standard and its Efficient Implementation on a DSP ProcessorZahid Khan, Tughrul Arslan, Scott MacDougall. 17-20 [doi]
• Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded MultipliersShuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois. 21-24 [doi]
• Architecture for Low Power Large Vocabulary Speech RecognitionDhruba Chandra, Ullas Pazhayaveetil, Paul D. Franzon. 25-28 [doi]
• A General Method to VLSI Polyphase Filter Analysis and Design for Integrated RF ApplicationsHongjiang Song. 31-34 [doi]
• I/Q-Channel Mismatch Transfer and Amplification Effects and Applications to the Measurement and Calibration of Integrated VLIF RF ReceiversHongjiang Song, Syed R. Naqvi, Bertan Bakkaloglu. 35-38 [doi]
• A Dual-Function Filter for 5.25GHZ Narrowband and 3.6GHZ-10.1GHZ Ultrawideband SystemsAnh Dinh, Bi Pham. 39-42 [doi]
• Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data CommunicationHongjiang Song. 43-46 [doi]
• H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based ArchitectureAdam Major, Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan. 49-52 [doi]
• A Compact and High Performance Switch for Circuit-Switched Network-On-ChipPhi-Hung Pham, Yogendera Kumar, Chulwoo Kim. 53-56 [doi]
• Cell Switched Network-on-Chip - Candidate for Billion-Transistor System-on-ChipsYuhua Chen. 57-60 [doi]
• An On-Chip Measurement Circuit for Calibration by Combination SelectionJanne Maunu, Joona Marku, Mika Laiho, Ari Paasio. 63-64 [doi]
• A Novel Mini-LVDS Receiver in 0.35-um CMOSChung-Yuan Chen, Jia-Hong Wang, Tai-Ping Sun. 65-68 [doi]
• A Reconfigurable CMOS Power Amplifier Operating from 0.9 TO 2.4 GHZ for WPAN ApplicationSeok-Oh Yun, Hyung-Joun Yoo. 69-72 [doi]
• A Pulse-Based Full-Band UWB Transceiver SoC in 0.18μm SiGe BiCMOSHaolu Xie, Siqiang Fan, Xin Wang, Albert Z. Wang, Zhihua Wang, Hongyi Chen. 73-76 [doi]
• Energy-Aware Code Replication for Improving Reliability in Embedded Chip MultiprocessorsGuilin Chen, Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir. 77-78 [doi]
• Optimal Multiple-Bit Huffman DecodingYa-Nan Wen, Sao-Jie Chen, Yu Hen Hu. 79-82 [doi]
• A Leakage Compensation Technique for Dynamic Latches and Flip-Flops in Nano-Scale CMOSMartin Hansson, Atila Alvandpour. 83-84 [doi]
• Stochastic Glitch Estimation and Path Balancing for Statistical OptimizationHosun Shin, Naeun Zang, Juho Kim. 85-88 [doi]
• Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A ComparisonRanjith Kumar, Volkan Kursun. 89-90 [doi]
• Analysis of Subthreshold Finfet Circuits for Ultra-Low Power DesignXiaoxia Wu, Feng Wang 0004, Yuan Xie. 91-92 [doi]
• Design of Ultra-Low Power Combinational Standard Library Cells Using A Novel Leakage Reduction MethodologyPreetham Lakshmikanthan, Karan Sahni, Adrian Nunez. 93-94 [doi]
• Method for Managing Electromigration in SOC'S When Designing for Both Reliability and ManufacturingKaren Chow, David Abercrombie, Mark Basel. 95-102 [doi]
• Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols and Matching InformationChangRyul Yun, Younghwan Bae, Hanjin Cho, KyoungSon Jhang. 103-104 [doi]
• Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAsPriya Sundararajan, Sridhar Krishnamurthy, Narayanan Vijaykrishnan, Kamal Chaudhary, Rajeev Jayaraman. 105-106 [doi]
• A Reconfigurable Viterbi Traceback for Implemenation on Turbo Decoding ArrayImran Ahmed, Tughrul Arslan. 107-108 [doi]
• SoC Design Space Exploration through Automated IP Selection from SystemC IP LibraryDeepak Mathaikutty, Sandeep K. Shukla. 109-110 [doi]
• A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image ProcessorsZhenyu Qi, Wei Huang, Adam C. Cabe, Wenqian Wu, Yan Zhang, Garrett S. Rose, Mircea R. Stan. 111-112 [doi]
• Geometric Tiling for Reducing Power Consumption in Structured Matrix OperationsG. Chen, Liping Xue, J. Kim, Kanwaldeep Sobti, Lanping Deng, Xiaobai Sun, Nikos Pitsianis, Chaitali Chakrabarti, Mahmut T. Kandemir, N. Vijaykhshnan. 113-114 [doi]
• High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline DecouplingZhiyu Liu, Volkan Kursun. 115-116 [doi]
• A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O CircuitsRui Tang, Yong-Bin Kim. 119-122 [doi]
• A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication SystemQingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski. 123-126 [doi]
• Reconfigurable Switched-Capacitor ΔΣ Modulator Topology DesignYing Wei, Pengbo Sun, Alex Doboli. 127-130 [doi]
• A 1.3 V 30-mW 8-BIT 166-MS/s A/D Converter in 0.18 μm CMOS with Reference GeneratorJing-hu Li, Ming-Yan Yu, Yong-sheng Wang, Jin-Xiang Wang. 131-134 [doi]
• Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon PrototypingChun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou. 137-140 [doi]
• VLSI Architecture for Encryption and Watermarking Units Towards the Making of a Secure CameraOluwayomi Adamo, Saraju P. Mohanty, Elias Kougianos, Murali R. Varanasi. 141-144 [doi]
• A Trace-Driven Validation Methodology for Multi-Processor SOCSJayanta Bhadra, Ekaterina Trofimova, Leonard J. Giordano, Magdy S. Abadir. 145-148 [doi]
• Embedded Controllers for Solving Complex Industry ApplicationsJuergen Saalmueller, Joerg Wuertz. 149-152 [doi]
• Low-Power and Process Variation Tolerant Memories in sub-90nm TechnologiesSaibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim, Kaushik Roy. 155-159 [doi]
• A low complexity, low power, programmable QRS detector based on wavelet transform for Implantable Pacemaker ICThanh-Tung Hoang, Jong-Pil Son, Yu-Ri Kang, Chae-Ryung Kim, Hae-Young Chung, Soo-Won Kim. 160-163 [doi]
• Leakage Reduction for Domino Circuits in Sub-65nm TechnologiesManjari Agarwal, Praveen Elakkumanan, Ramalingam Sridhar. 164-167 [doi]
• Applying ESL in A Dual-Core SoC Platform DesigningAlan P. Su, Robert Chen. 171-174 [doi]
• Bit-Width Aware High-Level Synthesis for Digital Signal Processing SystemsBertrand Le Gal, Caaliph Andriamisaina, Emmanuel Casseau. 175-178 [doi]
• Process Variation Aware Parallelization Strategies for MPSoCsSuresh Srinivasan, Raghavan Ramadoss, Narayanan Vijaykrishnan. 179-182 [doi]
• eXtreme Energy Conservation for Mobile CommunicationsChristopher K. Y. Chun. 185-188 [doi]
• Compiler Support for Voltage IslandsGuangyu Chen, Mahmut T. Kandemir, Mustafa Karaköy. 189-192 [doi]
• Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code CompressionBalaji Vaidyanathan, Yuan Xie. 193-196 [doi]
• Platform-Based Behavior-Level and System-Level SynthesisJason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang. 199-202 [doi]
• On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library StudyHuang-Liang Chen, Hung-Ming Chen. 203-206 [doi]
• Consideration of Transition-Time Variability in Statistical Timing AnalysisTakeshi Kouno, Hidetoshi Onodera. 207-210 [doi]
• Performance Constraints Aware Voltage Islands Generation in SoC Floorplan DesignMing-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, Iris Hui-Ru Jiang. 211-214 [doi]
• SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP ProcessorRaj Varada, Simon Tarn, John Benoit, Kris Chou. 217-220 [doi]
• Integration of Configurable Processors in a Multiprocessor PlatformSimon Provost, Bruno Lavigueur, Guy Bois, Gabriela Nicolescu. 221-224 [doi]
• Crosstalk-aware Energy Reduction in NoC Communication FabricsPartha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu. 225-228 [doi]
• Interrupt Communication on the SegBus platformAppaya Devaraj Swaminathan, Tiberiu Seceleanu. 229-232 [doi]
• Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip CostAkhil Garg, Prashant Dubey. 235-238 [doi]
• MTNET: Design and Optimization of a Wireless SOC Test FrameworkDan Zhao, Yi Wang 0007. 239-242 [doi]
• Modeling the Impact of Process Variation on Critical Charge DistributionQian Ding, Rong Luo, Hui Wang, Huazhong Yang, Yuan Xie. 243-246 [doi]
• A Trace Based Framework for Validation of SoC Designs with GALS SystemsSyed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla. 247-250 [doi]
• Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable MemoryNitin Mohan, Wilson Fung, Manoj Sachdev. 253-256 [doi]
• A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOSBehzad Mesgarzadeh, Atila Alvandpour. 257-260 [doi]
• Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS TechnologiesJoyce Yeung, Hamid Mahmoodi. 261-264 [doi]
• Architecture for Energy Efficient Sphere DecodingRavi Jenkal, Hao Hua, Ambarish M. Sule, W. Rhett Davis. 267-270 [doi]
• A Scalable Packet Sorting Circuit for High-Speed WFQ Packet SchedulingKieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll. 271-274 [doi]
• A Mimo Receiver SOC for CDMA ApplicationsTongtong Chen, Zhengtao Yu 0002, Yuantao Peng, Yanbing Zhang, Huaiyu Dai, Xun Liu. 275-278 [doi]
• Effects of Interconnect Process Variations on Signal IntegrityErtugrul Demircan. 281-284 [doi]
• 3-D Topologies for Networks-on-ChipVasilis F. Pavlidis, Eby G. Friedman. 285-288 [doi]
• A Low-swing Signaling Circuit Technique for 65nm On-chip InterconnectsVishak Venkatraman, Mark Anders, Himanshu Kaul, Wayne Burleson, Ram Krishnamurthy. 289-292 [doi]
• Substrate and Ground Noise Interactions in Mixed-Signal CircuitsEmre Salman, Eby G. Friedman, Radu M. Secareanu. 293-296 [doi]
• Cache Organization for Embeded Processors: CAM-vs-SRAMBaker Mohammad, Paul Bassett, Jacob A. Abraham, Adnan Aziz. 299-302 [doi]
• Memories: Exploiting Them and Developing ThemWilliam R. Reohr. 303-310 [doi]
• Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAMNitin Mohan, Manoj Sachdev. 311-314 [doi]
• A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM DesignMasanao Yamaoka, Hidetoshi Onodera. 315-318 [doi]
• Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCsMartin Margala. 321 [doi]
• High-performance energy-efficient memory circuit technologies for sub-45nm technologiesAmit Agarwal, Ram Krishnamurthy. 322 [doi]
• Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and OpportunitiesAzad Naeemi, Muhannad S. Bakir. 323-324 [doi]
• Design of Low Power Digital Phase Lock LoopsK. Nagaraj, N. Nayak. 325-326 [doi]
• Silicon Debug and DFT for SOC IPN. Dakwala. 327-328 [doi]
• On-Chip Distributed ArchitecturesTiberiu Seceleanu, Axel Jantsch, Hannu Tenhunen. 329-330 [doi]