Table of Contents

• Keynote speaker: Driving innovation in the "post-silicon" worldBernard S. Meyerson. 1-2 [doi]
• Plenary speaker: Low power solutions for a smarter futureRichard Grisenthwaite. 3 [doi]
• Plenary speaker: Era of SoCs: What is next?Raj Yavatkar. 4 [doi]
• An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operationMei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang. 5-10 [doi]
• An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensorKazuo Otsuga, Masafumi Onouchi, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, Kazumasa Yanagisawa. 11-14 [doi]
• A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptationSebastian M. Londono, José Pineda de Gyvez. 15-20 [doi]
• Variation-and-aging aware low power embedded SRAM for multimedia applicationsNa Gong, Shixiong Jiang, Anoosha Challapalli, Manpinder Panesar, Ramalingam Sridhar. 21-26 [doi]
• pbCAM: Probabilistically-banked Content Addressable MemoryTolga Soyata, John Liobe. 27-32 [doi]
• "Free" Razor: A novel adaptive voltage scaling low power technique for data path SoC designsYuejian Wu, Sandy Thomson, Han Sun, David Krause, Song Yu, George Kurio. 33-38 [doi]
• ADPLL variables determinations based on phase noise, spur and locking timeBo Jiang, Tian Xia. 39-44 [doi]
• A novel digital loop filter architecture for bang-bang ADPLLMoataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed AbdElSalam, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor. 45-50 [doi]
• A 1.7GS/s 6-bit Flash A/D converter with distributed offset cancelling sample-and-holdL. Mountrichas, Th. Laopoulos, Stilianos Siskos. 51-56 [doi]
• A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2Jin-Cheol Seo, Sang-Soon Im, Kwan Yoon, Seung-Wook Oh, Taek-Joon An, Gi-Yeol Bae, Jin-Ku Kang. 57-60 [doi]
• Gray-level image recognition on a dynamically reconfigurable vision architectureYuki Kamikubo, Minoru Watanabe, Shoji Kawahito. 61-65 [doi]
• A read-assist write-back voltage sense amplifier for low voltage-operated SRAMsTahseen Shakir, Manoj Sachdev. 66-71 [doi]
• Synthesizable delay line architectures for digitally controlled voltage regulatorsOmar Haridy, Harish Krishnamurthy, Amr Helmy, Yehea Ismail. 72-77 [doi]
• A novel design flow for a 3D heterogeneous system prototyping platformChun-Ming Huang, Chih-Chyau Yang, Chien-Ming Wu, Chun-Chieh Chiu, Yi-Jun Liu, Chun-Chieh Chiu, Nien-Hsiang Chang, Wen-Ching Chen, Chih-Hsing Lin, Hua-Hsin Luo. 78-82 [doi]
• An FPGA implementation for a high-speed optical link with a PCIe interfaceEdin Kadric, Naraig Manjikian, Zeljko Zilic. 83-87 [doi]
• Invited talk: Noise and mismatch in sub 28nm silicon processesAndrew Marshall. 88-93 [doi]
• Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancementMatthew Catanzaro, Dhireesha Kudithipudi. 94-99 [doi]
• Limitations of integrating field induced aggregation based fault repair automatons with integrated circuitsAveek Dutta, Sanjiv Sambandan. 100-103 [doi]
• Efficient generation of analog circuit models for accelerated mixed-signal simulationStefan Hoelldampf, H.-S. L. Lee, Daniel Zaum, Markus Olbrich, Erich Barke. 104-109 [doi]
• Neural recording system with low-noise analog front-end and comparator-based cyclic ADCSusie Kim, Seung-In Na, Tae Hoon Kim, Hyunjoong Lee, Sunkwon Kim, Cyuyeol Rhee, Suhwan Kim. 110-114 [doi]
• Methodology to determine dominant noise source in a system-on-chip based implantable deviceZhihua Gan, Emre Salman, Milutin Stanacevic. 115-119 [doi]
• A wide tuning range QCCO based on CMOS active inductorsJun Zhang, Huihua Liu. 120-124 [doi]
• Evaluation of layout design styles using a quality design metricSergio Gómez, Francesc Moll. 125-130 [doi]
• Lightweight energy prediction framework for solar-powered wireless sensor networksCory E. Merkel, Dhireesha Kudithipudi, Andres Kwasinski. 131-136 [doi]
• Design of near threshold All Digital Delay Locked LoopsMehdi Sadi, Mircea Stan. 137-142 [doi]
• A stable chip-ID generating physical uncloneable function using random address errors in SRAMHidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii. 143-147 [doi]
• STT-MRAM memory cells with enhanced on/off ratioRavi Patel, Engin Ipek, Eby G. Friedman. 148-152 [doi]
• Efficient high-speed current-mode links for network-on-chip performance optimizationHamed Sajjadi Kia, Cristinel Ababei. 153-158 [doi]
• Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposerLi Zheng, Muhannad S. Bakir. 159-164 [doi]
• Interconnect compression and its benefits for multi-core systemsJiangjiang Liu, Jianyong Zhang. 165-170 [doi]
• Ventti: A vertically integrated framework for simulation and optimization of networks-on-ChipYoung-Jin Yoon, Nicola Concer, Luca P. Carloni. 171-176 [doi]
• Reconfigurable framework for high-bandwidth stream-oriented data processingAlexander Mykyta, Dorin Patru, Eli Saber, Gene Roylance, Brad Larson. 177-183 [doi]
• A testability-aware low power architectureGang Wang, Jian Wang, Zi-Chu Qi. 184-189 [doi]
• Plenary speaker: Connectivity driven systems: On-chip, off-chip and in-betweenRobert E. Geer. 190-191 [doi]
• Multi-objective optimization of radio-frequency front-endsJosef Dobes, Jan Míchal, Viera Biolkova. 192-197 [doi]
• Continuous-time single-symbol IR-UWB symbol detectionShanthi Sudalaiyandi, Tuan Anh Vu, Håkon A. Hjortland, Øivind Næss, Tor Sverre Lande. 198-201 [doi]
• A 1Gbps FPGA-based wireless baseband MIMO transceiverCiaran Toal, Sakir Sezer, Dwayne Burns, Pei Xaio, Vincent F. Fusco. 202-207 [doi]
• Implementation of a network flow lookup circuit for next-generation packet classifiersXin Yang, Sakir Sezer. 208-212 [doi]
• Design of a sensor node crypto processor for IEEE 802.15.4 applicationsGoran Panic, Thomas Basmer, Schomann Henry, Steffen Peter, Frank Vater, Klaus Tittelbach-Helmrich. 213-217 [doi]
• A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assistYung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu. 218-223 [doi]
• Low power 6T-SRAM with tree address decoder using a new equalizer precharge schemeYuan Ren, Michael Gansen, Tobias G. Noll. 224-229 [doi]
• Efficient, snoopless, System-on-Chip coherenceStefanos Kaxiras, Alberto Ros. 230-235 [doi]
• SOLARCAP: Super capacitor buffering of solar energy for self-sustainable field systemsAmal Fahad, Tolga Soyata, Tai Wang, Gaurav Sharma, Wendi B. Heinzelman, Kai Shen. 236-241 [doi]
• An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocksUpasna Vishnoi, Michael Meixner, Tobias G. Noll. 242-247 [doi]
• Workload and task characterization based on operation modes timing analysisA. Patino A. Gustavo, Jorge Gonzalez, Wang Jiang Chau, Marius Strum. 248-253 [doi]
• Direction-constrained layer assignment for rectangle escape routingJin-Tai Yan, Zhi-Wei Chen. 254-259 [doi]
• Schematic-driven physical verification: Fully automated solution for analog IC designAhmed Arafa, Hend Wagieh, Rami Fathy Salem, John Ferguson, Doug Morgan, Mohab H. Anis, Mohamed Dessouky. 260-264 [doi]
• Multi-Clock DFT architecture for interface characterization and powerChristopher Ryan, Kris Monsen, Scott Smith, Henry So. 265-270 [doi]
• Optimal power-constrained SoC test schedules with customizable clock ratesVijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal. 271-276 [doi]
• Efficient fault emulation using automatic pre-injection memory access analysisJohannes Grinschgl, Armin Krieg, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 277-282 [doi]
• Mutation-analysis driven functional verification of a soft microprocessorTao Xie, Wolfgang Müller 0003, Florian Letombe. 283-288 [doi]
• Intellectual property protection and security of SoCs - An embedded tutorialSusmita Sur-Kolay. 289 [doi]
• Neuromorphic computing: A SoC scaling path for the next decadesYiran Chen, Qing Wu. 290-291 [doi]
• Exploiting memristive device behavior for emerging digital logic and memory applicationsGarret S. Rose. 292 [doi]
• A massive parallel neuromorphic computing model for intelligent text recognitionQinru Qiu. 293 [doi]
• Memristor in neuromorphic computingHai Helen Li. 294 [doi]
• A power-area analysis of NoCs in FPGAsM. Binesh Marvasti, Ted H. Szymanski. 295-300 [doi]
• DVFS-enabled sustainable wireless NoC architectureJacob Murray, Partha Pratim Pande, Behrooz Shirazi. 301-306 [doi]
• Design space exploration for robust power delivery in TSV based 3-D systems-on-chipSuhas M. Satheesh, Emre Salman. 307-311 [doi]
• A scalable electrical characterization method for inter-strata interconnects in 3-D ICsTian Xia, Guoan Wang. 312-316 [doi]
• Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PACHsien-Ching Hsieh, Po-Han Huang, Chi-Hung Lin, Huang-Lun Lin. 317-321 [doi]
• Aging-aware reliable multiplier designYu-Hung Cho, Ing-Chao Lin, Yi-Ming Yang. 322-327 [doi]
• A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learningYongtae Kim, Yong Zhang, Peng Li. 328-333 [doi]
• A novel flexible foldable systolic architecture FIR filters generatorHang Yin, Weitao Du, Yu Hen Hu, Rui Lv. 334-339 [doi]
• A sensor-less NBTI mitigation methodology for NoC architecturesDavide Zoni, William Fornaciari. 340-345 [doi]
• Design of a scalable RF microarchitecture for heterogeneous MPSoCsDan Zhao, Yi Wang 0007. 346-351 [doi]
• Design of an NoC with on-chip photonic interconnects using adaptive CDMA linksSoumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman. 352-357 [doi]
• Design of interlock-free combined allocators for Networks-on-ChipYe Lu, Changlin Chen, John V. McCanny, Sakir Sezer. 358-363 [doi]
• MAZENOC: Novel approach for fault-tolerant NOC routingEduardo Weber Wächter, Fernando Gehm Moraes. 364-369 [doi]
• On-chip self-calibrated process-temperature sensor for TSV 3D integrationTzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang. 370-375 [doi]
• Calibration of propagation delay of flip-flopsTamer Ragheb, Andrew Marshall. 376-380 [doi]
• Native-conflict-avoiding track routing for double patterning technologyBi-Ting Lai, Tai-Hung Li, Tai-Chen Chen. 381-386 [doi]
• Variation tolerant self-adaptive clock generation architecture based on a ring oscillatorJordi Perez-Puigdemont, Antonio Calomarde, Francesc Moll. 387-392 [doi]