Abstract is missing.
- Formal Verification of Pipelined ProcessorsRandal E. Bryant. 1-4 [doi]
- Fully Local and Efficient Evaluation of Alternating Fixed Points (Extended Abstract)Xinxin Liu, C. R. Ramakrishnan, Scott A. Smolka. 5-19 [doi]
- Modular Model Checking of SoftwareKaren Laster, Orna Grumberg. 20-35 [doi]
- Verification Based on Local StatesMichaela Huhn, Peter Niebert, Frank Wallner. 36-51 [doi]
- Exploiting Symmetry in Linear Time Temporal Logic Model Checking: One Step BeyondKhalil Ajami, Serge Haddad, Jean-Michel Ilié. 52-67 [doi]
- OPEN/CÆSAR: An OPen Software Architecture for Verification, Simulation, and TestingHubert Garavel. 68-84 [doi]
- Practical Model-Checking Using GamesPerdita Stevens, Colin Stirling. 85-101 [doi]
- Combining Finite Automata, Parallel Programs and SDL Using Petri NetsBernd Grahlmann. 102-117 [doi]
- MESA: Support for Scenario-Based Design of Concurrent SystemsHanêne Ben-Abdallah, Stefan Leue. 118-135 [doi]
- Efficient Modeling of Memory Arrays in Symbolic Ternary SimulationMiroslav N. Velev, Randal E. Bryant. 136-150 [doi]
- Translation ValidationAmir Pnueli, Michael Siegel, Eli Singerman. 151-166 [doi]
- A Verified Model Checker for the Modal µ-calculus in CoqChristoph Sprenger. 167-183 [doi]
- Detecting Races in Relay Ladder Logic ProgramsAlexander Aiken, Manuel Fähndrich, Zhendong Su. 184-200 [doi]
- Verification of Large State/Event Systems Using Compositionality and Dependency AnalysisJørn Lind-Nielsen, Henrik Reif Andersen, Gerd Behrmann, Henrik Hulgaard, Kåre J. Kristoffersen, Kim Guldstrand Larsen. 201-216 [doi]
- Tamagotchis Need Not Die - Verification of STATEMENT DesignUdo Brockmeyer, Gunnar Wittich. 217-231 [doi]
- Modeling and Verification of SC++ ApplicationsThierry Cattel. 232-248 [doi]
- Factotum: Automatic and Systematic Sharing Support for Systems AnalyzersDavid James Sherman, Nicolas Magnier. 249-262 [doi]
- Model Checking via Reachability Testing for Timed AutomataLuca Aceto, Augusto Burgueño, Kim Guldstrand Larsen. 263-280 [doi]
- Formal Design and Analysis of a Gear ControllerMagnus Lindahl, Paul Pettersson, Wang Yi. 281-297 [doi]
- Verifying Networks of Timed Processes (Extended Abstract)Parosh Aziz Abdulla, Bengt Jonsson. 298-312 [doi]
- Model Checking of Real-Time Reachability Properties Using AbstractionsConrado Daws, Stavros Tripakis. 313-329 [doi]
- Symbolic Exploration of transition HierarchiesRajeev Alur, Thomas A. Henzinger, Sriram K. Rajamani. 330-344 [doi]
- Static Partial Order ReductionRobert P. Kurshan, Vladimir Levin, Marius Minea, Doron Peled, Hüsnü Yenigün. 345-357 [doi]
- Set-Based Analysis of Reactive Infinite-State SystemsWitold Charatonik, Andreas Podelski. 358-375 [doi]
- Deiding Fixed and Non-fixed Size Bit-vectorsNikolaj Bjørner, Mark C. Pichora. 376-392 [doi]
- Experience with Literate Programming in the Modelling and Validation of SystemsTheo C. Ruys, Ed Brinksma. 393-408 [doi]
- A Proof of Burns ::::N::::-Process Mutual Exclusion Algorithm Using AbstractionHenrik Ejersbo Jensen, Nancy A. Lynch. 409-423 [doi]
- Automated Verification of Szymanski s AlgorithmE. Pascal Gribomont, Guy Zenner. 424-438 [doi]
- Formal Verification of SDL Systems at the Siemens Mobile Phone DepartmentFranz Regensburger, Aenne Barnard. 439-455 [doi]