Abstract is missing.
- Design challenges for the 45 nm node and belowJean-Pierre Schoellkopf. [doi]
- The system is really in the SoC : new investment opportunitiesJacques Benkowski. [doi]
- An overview of where the fields of SoCs, HDI and MEMS are heading to and how to characterize themA. Domman. [doi]
- Introduction to panel discussion Probabilistic & statistical design - the wave of the futureShekhar Borkar. [doi]
- Probabilistic CMOS Technology: A Survey and Future DirectionsBilge E. S. Akgul, Lakshmi N. Chakrapani, Pinar Korkmaz, Krishna V. Palem. 1-6 [doi]
- Can Asynchronous Techniques Help the SoC Designer?Alain J. Martin. 7-11 [doi]
- State-holding in Look-Up Tables: application to asynchronous logicLaurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin. 12-17 [doi]
- MDCT IP Core Generator with Architectural Model SimulationPeter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík. 18-23 [doi]
- A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architecturesMarco Giorgetta, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini. 24-29 [doi]
- Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction MergingAntonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro. 30-35 [doi]
- Architectures for High Dynamic Range, High Speed Image Sensor Readout CircuitsSam Kavusi, Kunal Ghosh, Abbas El Gamal. 36-41 [doi]
- Circuit and Device Technologies for CMOS functional Image SensorsShoji Kawahito. 42-47 [doi]
- Oversampled Time Estimation Techniques for Precision Photonic DetectorsRobert Henderson, Bruce Rae, David Renshaw, E. Charbon. 48-51 [doi]
- Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTVArnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi. 52-57 [doi]
- High-Throughput Montgomery Modular MultiplicationRamachandruni Venkata Kamala, M. B. Srinivas. 58-62 [doi]
- A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion EstimationSinan Yalcin, Ilker Hamzaoglu. 63-67 [doi]
- An Efficient Scheduler for Circuit-Switched Network-on-Chip ArchitecturesHsin-Chou Chi, Chia-Ming Wu. 68-73 [doi]
- Fast IP-Core Generation in a Partial Dynamic Reconfiguration WorkflowMatteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. 74-79 [doi]
- Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on ChipChris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen. 80-85 [doi]
- A High Performance SoC On-chip-bus with Multiple Channels and Routing ProcessesSanghun Lee, Chanho Lee. 86-91 [doi]
- Signal Coverage Computation in Formal VerificationHamid Shojaei, Mohammad Sayyaran. 92-97 [doi]
- Modelling Heterogeneous Interactions in SoC VerificationJustin Xu, Cheng-Chew Lim. 98-103 [doi]
- PEACH: A Novel Architecture for Probabilistic Combinational Equivalence CheckingShih-Chieh Wu, Chun-Yao Wang. 104-109 [doi]
- A Fast SAT Solver Strategy Based on Negated ClausesRomanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.. 110-115 [doi]
- On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real SystemsChin-Cheng Kuo, Chien-Nan Jimmy Liu. 116-121 [doi]
- Variation-Aware, Library Compatible Delay Modeling StrategyLuís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira. 122-127 [doi]
- An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-ViasRenato Fernandes Hentschke, Sandro Sawicki, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis. 128-133 [doi]
- A VHDL Generation Tool for Optimized Parallel FIR FiltersVagner S. Rosa, Eduardo Costa, Sergio Bampi. 134-139 [doi]
- A Complete Multi-Processor System-on-Chip FPGA-Based Emulation FrameworkPablo Garcia Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli. 140-145 [doi]
- An Application Mapping Methodology and Case Study for Multi-Processor On-Chip ArchitecturesGiovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane. 146-151 [doi]
- A Predictable Communication Scheme for Embedded Multiprocessor SystemsDerin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici. 152-157 [doi]
- Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on ChipsSrinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo. 158-163 [doi]
- Detecting DNA by field effect transistor arraysUlrich Bockelmann. 164-168 [doi]
- Innovative Optoelectronic Approaches to Biomolecular Analysis with Arrays of Silicon DevicesCarlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, A. Nascetti, D. Caputo, G. de Cesare. 169-174 [doi]
- Human++: Emerging Technology for Body Area NetworksBert Gyselinckx, R. Vullers, C. Van Hoof, Julien Ryckaert, R. F. Yazicioglu, P. Fiorini, V. Leonov. 175-180 [doi]
- Security evaluation of dual rail logic against DPA attacksAlin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin. 181-186 [doi]
- A low power high performance CMOS voltage-mode quaternary full adderRicardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro. 187-191 [doi]
- A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video ProcessingJunichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno. 192-197 [doi]
- Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable DeviceMotoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi. 198-203 [doi]
- Efficient Power Management Strategy of FPGAs Using a Novel Placement TechniqueKostas Siozios, Dimitrios Soudris, Antonios Thanailakis. 204-209 [doi]
- High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT ProcessorSenthamaraikannan Raghunath, Syed M. Aziz. 210-215 [doi]
- A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technologyXue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai. 216-221 [doi]
- Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based ArchitectureSujan Pandey, Nurten Utlu, Manfred Glesner. 222-227 [doi]
- Architecture of an HDTV Intraframe Predictor for a H.264 DecoderWagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi. 228-233 [doi]
- Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML CellsStéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer. 234-238 [doi]
- BIST Scheme for Low Heat Dissipation and Reduced Test Application TimeM. Shah, D. Nagchoudhuri. 239-244 [doi]
- The Demand and Practical Approach for 100x Test CompressionRon Press, Jay Jahangiri. 245-250 [doi]
- Design of a Reconfigurable Multiprocessor Core for Higher Performance and Reliability of Embedded SystemsRavindra V. Kshirsagar, Rajendra M. Patrikar. 251-254 [doi]
- Directed Convergence Heuristic: A fast & novel approach to Steiner Tree ConstructionShampa Chakraverty, Arvind Batra, Aman Rathi. 255-260 [doi]
- Technical Documentation of Software and Hardware in Embedded SystemsBeate Muranko, Rolf Drechsler. 261-266 [doi]
- Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta ModulatorRamon Tortosa Navas, Antonio Aceituno, José Manuel de la Rosa, Francisco V. Fernández, Ángel Rodríguez-Vázquez. 267-271 [doi]
- Pseudo Floating-Gate Inverter with Feedback ControlYngvar Berg, Omid Mirmotahari, Snorre Aunet. 272-277 [doi]
- Main Memory Energy Optimization for Multi-Task ApplicationsHanene Ben Fradj, Cécile Belleudy, Michel Auguin. 278-283 [doi]
- EXOR Projected Sum of ProductsAnna Bernasconi, Valentina Ciriani, Roberto Cordone. 284-289 [doi]
- Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable ArchitecturesIttetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 290-295 [doi]
- Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus SynthesisSujan Pandey, Tudor Murgan, Manfred Glesner. 296-301 [doi]
- Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and RepeatersTudor Murgan, O. Mitrea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner. 302-307 [doi]
- A New Test Generation Model for Broadside Transition Testing of Partial Scan CircuitsTsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara. 308-313 [doi]
- Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL DescriptionsMargrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes. 314-319 [doi]
- CAT platform for analogue and mixed-signal test evaluation and optimizationAhcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu. 320-325 [doi]
- Study of a BIST Technique for CMOS Active Pixel SensorsLivier Lizzarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur. 326-331 [doi]
- Soft Error Resilient System Design through Error CorrectionSubhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim. 332-337 [doi]
- Organic Computing at the System on Chip LevelAbdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel. 338-341 [doi]
- Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system designAntonis Papanikolaou, Miguel Miranda, Hua Wang, Francky Catthoor, M. Satyakiran, Pol Marchal, Ben Kaczer, C. Bruynseraede, Zsolt Tokei. 342-347 [doi]
- A New Phase Noise Model for TSPC based dividerXiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo. 348-351 [doi]
- A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCsShan Jiang, Manh Anh Do, Kiat Seng Yeo. 352-356 [doi]
- A 5.4-GHz Low-Power Swallow-Conterless Frequency Synthesizer with a Nonliear PFDYue-Fang Kuo, Ro-Min Weng, Chun-Yu Liu. 357-360 [doi]
- Energy-Effcient Scheduling for Autonomous Mobile RobotsJeff Brateman, Changjiu Xian, Yung-Hsiang Lu. 361-366 [doi]
- Sleepy Keeper: a New Approach to Low-leakage Power VLSI DesignSe Hun Kim, Vincent John Mooney. 367-372 [doi]
- System-level Dynamic Power Management Techniques for Communication Intensive DevicesRodrigo M. Passos, José Augusto Miranda Nacif, Raquel A. F. Mini, Antonio Alfredo Ferreira Loureiro, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.. 373-378 [doi]
- Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog ComputationZeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz. 379-384 [doi]
- SOC Debug Challenges and ToolsK. Schultz, K. Paranjape. 385-390 [doi]
- Reduced Instrumentation and Optimized Fault Injection Control for Dependability AnalysisPierre Vanhauwaert, Régis Leveugle, Philippe Roche. 391-396 [doi]
- On-Line Test Vector Generation from Temporal Constraints Written in PSLYann Oddos, Katell Morin-Allory, Dominique Borrione. 397-402 [doi]
- Structural-Based Power-Aware Assignment of Don t Cares for Peak Power Reduction during Scan TestingNabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich. 403-408 [doi]