Table of Contents

• Power Reduction Techniques for Portable DSP ApplicationsMahesh Mehendale, Sunil D. Sherlekar. 3
• Theory and Applications of Cellular Automata for VLSI Design and TestingParimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar. 4
• Test Techniques and Trade-offs for Embedded Cores and SystemsRubin A. Parekhji. 5
• Computer-aided Design of RF Communication Systems: Techniques and ChallengesLaurence Nagel, Jaijeet S. Roychowdhury. 6
• Analog Circuits for Wireless CommunicationsRamesh Harjani. 7
• New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits8
• Core Based ASIC DesignFrank P. Higgins, Sudipta Bhawmik. 10
• Partition, Packing and Clock Distribution-A New Paradigm of Physical DesignYoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake. 11
• Low Power VLSI Signal ProcessingKaushik Roy, Khurram Muhammad. 12
• Computing and Communication in the New MillenniumAvtar Saini. 15
• EDA-The Next GenerationAjoy K. Bose. 19
• IP Reuse in System on a Chip DesignRaul Camposano, Warren Savage, John Chilton. 20
• Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICsLiqiong Wei, Kaushik Roy, Vivek De. 24-29 [doi]
• Low Power Realization of Residue Number System Based FIR FiltersM. N. Mahesh, Mahesh Mehendale. 30-33 [doi]
• An Assertion Based Technique for Transistor Level Dynamic Power EstimationSavithri Sundareswaran, R. Venkatesan, S. Bhaskar. 34-37 [doi]
• Relating Data Characteristics to Transition Activity in High-Level Static CMOS DesignRussell Henning, Chaitali Chakrabarti. 38-43 [doi]
• A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI TechnologyRajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang. 44-49 [doi]
• Energy Aware SoftwareAmit Sinha, Anantha Chandrakasan. 50 [doi]
• Performance and Functional Verification of MicroprocessorsPradip Bose, Jacob A. Abraham. 58-63 [doi]
• Automatic Component Matching Using Forced SimulationPartha S. Roop, Arcot Sowmya, S. Ramesh. 64-69 [doi]
• Status Condition Analysis during Data Path Verification of Sequential CircuitsDipankar Sarkar. 70-75 [doi]
• Modeling VHDL in Multiclock ESTERELBasant Rajan, R. K. Shyamasundar. 76-83 [doi]
• Formal Verification of Synthesized Mixed Signal Designs Using *BMDsAbhijit Ghosh, Ranga Vemuri. 84 [doi]
• nterface Synthesis: Issues and ApproachesArvind Rajawat, M. Balakrishnan, Anshul Kumar. 92 [doi]
• Processor Evaluation in an Embedded Systems Design EnvironmentT. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik. 98-103 [doi]
• Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation KernelRainer Schaffer, Renate Merker, Francky Catthoor. 104-109 [doi]
• Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic ProgrammingAviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan. 110-113 [doi]
• COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server SystemsRobert P. Dick, Niraj K. Jha. 114 [doi]
• Challenges of Merging Digital Imaging and Wireless CommunicationWerner Metz, Tinku Acharya. 122-127 [doi]
• Design of an ASIC for Straight Line Detection in an ImageArun K. Majumdar, Nirav Patel. 128-133 [doi]
• Digital Imaging with Wireless Data ServicesSandip Sarkar. 134-139 [doi]
• GF(2p) CA Based Vector Quantization for Fast Encoding of Still ImagesKolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury. 140-143 [doi]
• Scalable Pipelined Micro-Architecture for Wavelet TransformKolin Paul, Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury. 144 [doi]
• Interconnect Statistical Modeling: Structures and Measurement MethodologiesAkis Doganis. 150 [doi]
• Design and Analysis of Power Distribution Networks with Accurate RLC ModelsRajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw. 151-155 [doi]
• A Methodology for the Placement and Optimization of Decoupling Capacitors for Gigahertz SystemsJinseong Choi, Sungjun Chun, Nanju Na, Madhavan Swaminathan, Larry Smith. 156-161 [doi]
• Inductive Noise Reduction at the Architectural LevelMondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari. 162-167 [doi]
• Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS CircuitsShiyou Zhao, Kaushik Roy. 168 [doi]
• Manufacturing and Test Considerations in System-On-Chip DesignsManuel A. d Abreu. 176-177 [doi]
• Cost Trade-Offs in System On Chip DesignsJitendra Khare, Hans T. Heineken, M. d Abreu. 178-184 [doi]
• Manufacturability and Testability Oriented SynthesisSaghir A. Shaikh, Jitendra Khare, Hans T. Heineken. 185-191 [doi]
• Maximizing Wafer Productivity Through Layout OptimizationCharles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, M. d Abreu. 192-197 [doi]
• Hierarchical Test Generation for Systems On a ChipRaghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab. 198 [doi]
• A Genetic Algorithm for the Synthesis of Structured Data PathsChittaranjan A. Mandal, R. M. Zimmer. 206-211 [doi]
• A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device ArchitecturesSriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri. 212-219 [doi]
• High-Level Synthesis with Variable-Latency ComponentsVijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana. 220-227 [doi]
• CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath SynthesisVamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan. 228-233 [doi]
• Design Partitioning on Single-Chip Emulation SystemsAbdel Ejnioui, N. Ranganathan. 234-239 [doi]
• Delay-Constrained Area Recovery Via Layout-Driven Buffer OptimizationRajeev Murgai. 240 [doi]
• Routing on Switch Matrix Multi-FPGA SystemsAbdel Ejnioui, N. Ranganathan. 248-253 [doi]
• A Transistor Level Placement Tool for Custom Cell GenerationRanjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna. 254-257 [doi]
• On the Transistor Sizing ProblemAbhijit Das. 258-261 [doi]
• Evaluation of Various Routing Architectures for Multi-FPGA BoardsSushil Chandra Jain, Shashi Kumar, Anshul Kumar. 262-267 [doi]
• A Fast Graph-Based Alternative Wiring Scheme for Boolean NetworksYu-Liang Wu, Wangning Long, Hongbing Fan. 268-273 [doi]
• Topological Routing Amidst Polygonal ObstaclesSwarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya. 274-279 [doi]
• A Tight Area Upper Bound for Slicing FloorplansHelvio P. Peixoto, Margarida F. Jacome, Ander Royo. 280 [doi]
• A New Definition and a New Class of Sequential Circuits with Combinational Test Generation ComplexityHideo Fujiwara. 288-293 [doi]
• Test Transformation to Improve Compaction by Statistical EncodingHideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy. 294-299 [doi]
• Design for Strong Testability of RTL Data Paths to Provide Complete Fault EfficiencyHiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara. 300-305 [doi]
• Choice of Tests for Logic Verification and Equivalence CheckingVishwani D. Agrawal. 306-311 [doi]
• Automatic Validation Test Generation Using Extracted Control ModelsRobert W. Sumners, Jayanta Bhadra, Jacob A. Abraham. 312 [doi]
• DSP-The Real Time Technology for the New MillenniumJohn Scarisbric. 321
• Surviving the SOC Revolution: The Platform Approach to SOC DesignGrant Martin. 325
• A Fast Algorithm for Computing the Euler Number of an Image and its VLSI ImplementationSabyasachi Dey, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya. 330-335 [doi]
• Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLDRajesh T. N. Rajaram, Vinita Vasudevan. 336-341 [doi]
• A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection CapabilityBedabrata Pain, Guang Yang, Monico Ortiz, Kenneth McCarty, Julie Heynssens, Bruce Hancock, Thomas Cunningham, Chris Wrigley, Charlie Ho. 342-349 [doi]
• Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television ApplicationsSantanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra. 350-359 [doi]
• Specification and Design of a Quasi-Delay-Insensitive Java CardFu-Chiung Cheng, Chuin-Ren Wang. 356-361 [doi]
• Trends in Communication Technology and its Impact on SemiconductorSantanu Das. 362 [doi]
• Capturing the Effect of Crosstalk on DelaySachin S. Sapatnekar. 364-369 [doi]
• A Practical Approach to Crosstalk Noise Verification of Static CMOS DesignsN. S. Nagaraj, Frank Cano, Duane Young, Deepak Vohra, Manoj Das. 370-375 [doi]
• Inductance Characterization of Small Interconnects Using Test-Signal MethodJeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal. 376 [doi]
• Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded CoresBhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel. 382-391 [doi]
• On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 392-397 [doi]
• Resource-Constrained Compaction of Sequential Circuit Test SetsSurendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy. 398-405 [doi]
• Testing Flash MemoriesMohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap. 406-411 [doi]
• A Versatile BIST Technique Combining Test Registers and AccumulatorsFrank Mayer, Albrecht P. Stroele. 412 [doi]
• Dataflow Analysis for Resource Contention and Register Leakage PropertiesSubir K. Roy, Hiroaki Iwashita, Tsuneo Nakata. 418-423 [doi]
• Retargetable Functional Simulator Using High Level Processor ModelsSubhash Chandra, Rajat Moona. 424-429 [doi]
• State-Machine Based Logic Simulation Using Three Logic ValuesPeter M. Maurer, William J. Schilp. 430-435 [doi]
• Hierarchical Error Diagnosis Targeting RTL CircuitsVamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita. 436-441 [doi]
• Fast Error Diagnosis for Combinational VerificationAarti Gupta, Pranav Ashar. 442-448 [doi]
• Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration ArchitectureYang Xia, Pranav Ashar. 449 [doi]
• Efficient Implementation of ADPCM CodecAnil Sharma, C. P. Ravikumar. 456-461
• Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based SystemsC. P. Ravikumar, Gaurav Chandra, Ashutosh Verma. 462-467 [doi]
• A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor CoresKarthikeyan Madathil, Jagdish C. Rao, Subash G. Chandar, Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar. 468 [doi]
• SOI Digital Circuits: Design IssuesRuchir Puri, Ching-Te Chuang. 474-479 [doi]
• Jitter Estimation Methodology for Clock ChipsSanjeev Kumar Maheshwari, R. S. Krishanan, G. S. Visweswaran. 480-482 [doi]
• A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O BufferSanjeev Kumar Maheshwari, G. S. Visweswaran. 484-487 [doi]
• Silicon Heterostructure Devices for RF Wireless CommunicationB. Senapati, C. K. Maiti, Nirmal B. Chakrabarti. 488-491 [doi]
• Design of OTA Based Field Programmable Analog ArrayBaidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi. 492-497 [doi]
• Convergence Issues in Resonant Tunneling Diode Circuit SimulationMayukh Bhattacharya, Pinaki Mazumder. 499 [doi]
• Spectral Theory of Disjunctive Decomposition for Balanced Boolean FunctionsBogdan J. Falkowski, Sudha Kannurao. 506-511 [doi]
• Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area ReductionB. Suresh, Biswadeep Chaterjee, R. Harinath. 512-517 [doi]
• Timing Analysis with Implicitly Specified False PathsEugene Goldberg, Alexander Saldanha. 518-522 [doi]
• Clock Selection for Performance Optimization of Control-Flow Intensive BehaviorsKamal S. Khouri, Niraj K. Jha. 523-529 [doi]
• Performance Analysis of Systems with Multi-Channel Communication ArchitecturesKanishka Lahiri, Sujit Dey, Anand Raghunathan. 530-537 [doi]
• An ASIC for Cellular Automata Based Message AuthenticationPrabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta. 538 [doi]
• Cellular Automata Based Deterministic Test Sequence Generator for Sequential CircuitsPrabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta. 544-549 [doi]
• An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal BoardsSasikumar Cherubal, Abhijit Chatterjee. 550-555 [doi]
• Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern GeneratorBiplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee. 556-561 [doi]
• Application of GF(2p) CA in Burst Error Correcting CodesKolin Paul, Dipanwita Roy Chowdhury. 562-567 [doi]
• Built-In Self-Test in Mixed-Signal ICs: A DTMF MacrocellGloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas. 568-571 [doi]
• A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and CountersJeongjin Roh, Jacob A. Abraham. 572 [doi]
• Design of Synchronous Action SystemsJuha Plosila, Tiberiu Seceleanu. 578-583 [doi]