Table of Contents

• A Decade of Platform-Based Design: A look backwards, a look forwardsGrant Martin. 3 [doi]
• Analog IC Design in Nanometer CMOS TechnologiesWilly M. C. Sansen. 4 [doi]
• Common Power Format: A User-driven Ecosystem For Proven Low Power Design FlowsSumit Dasgupta. 5 [doi]
• The Future of Low Power Design is Here: IEEE P1801, aka, UPF 2.0Stephen Bailey. 6 [doi]
• Making Sense Out of the Potential Babble of Low Power StandardsGary Delp. 7 [doi]
• DFX and ProductivityRobert C. Aitken. 8 [doi]
• Computational Lithography - Moore Bang for your BuckVivek Singh. 9 [doi]
• Made for India ForumRajiv Kapur. 13 [doi]
• Why is Design Automation and Reuse of Analog Designs Increasingly Trailing the Digital World?Ghasi Agarwal, Prakash Bare. 17 [doi]
• EDA Made-in-India: Fact or Fiction?Raman Santhanakrishnan, Yatin Trivedi. 18 [doi]
• Solutions for a small car - Made for India and Made in India19 [doi]
• Accelerating Embedded System Design20 [doi]
• Defect Aware to Power Conscious Tests - The New DFT LandscapeNilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. 23-25 [doi]
• Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal CircuitsJaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín. 26-27 [doi]
• Power Reduction Techniques and Flows at RTL and System LevelAnmol Mathur, Qi Wang. 28-29 [doi]
• Security and Dependability of Embedded Systems: A Computer Architects PerspectiveJörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel. 30-32 [doi]
• Design for Manufacturability and Reliability in Nano EraGoutam Debnath, Paul J. Thadikaran. 33-34 [doi]
• Negative Feedback System and Circuit DesignNagendra Krishnapura, Shanthi Pavan. 35-36 [doi]
• Synthesis & Testing for Low PowerAjit Pal, Santanu Chattopadhyay. 37-38 [doi]
• Power Management for Mobile Multimedia: From Audio to Video & GamesSamarjit Chakraborty, Ye Wang. 39-40 [doi]
• Robust Circuit Design: Challenges and SolutionsSaurabh K. Tiwary, Amith Singhee, Vikas Chandra. 41-42 [doi]
• Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable DatapathSohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala. 45-50 [doi]
• Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN ChannelsWeihuang Wang, Gwan S. Choi, Kiran K. Gunnam. 51-56 [doi]
• Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using Dual Real-Time FeedbackMuhammad Mudassar Nisar, Abhijit Chatterjee. 57-62 [doi]
• Efficient Techniques for Directed Test Generation Using Incremental SatisfiabilityPrabhat Mishra, Mingsong Chen. 65-70 [doi]
• Inline Assertions - Embedding Formal Properties in a Test BenchAritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti. 71-76 [doi]
• Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTLVinod Viswanath, Shobha Vasudevan, Jacob A. Abraham. 77-82 [doi]
• A Novel Approach for Improving the Quality of Open Fault DiagnosisKoji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume. 85-90 [doi]
• Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm ICHiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu. 91-96 [doi]
• Efficient Grouping of Fail Chips for Volume Yield DiagnosticsLavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi. 97-102 [doi]
• 100KHz-20MHz Programmable Subthreshold G::m::-C Low-Pass Filter in 0.18µ-m CMOSS. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya. 105-110 [doi]
• A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6µm CMOSTheja Tulabandhula, Yujendra Mitikiri. 111-116 [doi]
• Design of a Low Power, Variable-Resolution Flash ADCSreehari Veeramachaneni, A. Mahesh Kumar, Venkat Tummala, M. B. Srinivas. 117-122 [doi]
• Floorplanning for Partial Reconfiguration in FPGAsPritha Banerjee, Megha Sangtani, Susmita Sur-Kolay. 125-130 [doi]
• Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog CircuitsAlmitra Pradhan, Ranga Vemuri. 131-136 [doi]
• Efficient Analog/RF Layout Closure with Compaction Based LegalizationSubramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala. 137-142 [doi]
• Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and ReconfigurationTameesh Suri, Aneesh Aggarwal. 145-150 [doi]
• Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-ChipsAmir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram. 151-156 [doi]
• Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on ChipsAmir-Mohammad Rahmani, I. Kamali, Pejman Lotfi-Kamran, Ali Afzali-Kusha, Saeed Safari. 157-162 [doi]
• Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture ExplorationBasavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur. 163-168 [doi]
• A Low Voltage CMOS Proportional-to-Absolute Temperature Current ReferenceSanjay Kumar Wadhwa. 171-174 [doi]
• Novel MOS Decoupling Capacitor Optimization Technique for NanotechnologiesBardia Bozorgzadeh, Ali Afzali-Kusha. 175-180 [doi]
• Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output RippleTamal Das, Pradip Mandal. 181-186 [doi]
• Reversible Logic Synthesis with Output PermutationRobert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler. 189-194 [doi]
• Cone Resynthesis ECO Methodology for Multi-Million Gate DesignsSuresh Raman, Mike Lubyanitsky. 195-199 [doi]
• A General Approach to High-Level Energy and Performance Estimation in SoCsSandro Penolazzi, Ahmed Hemani, Luca Bolognino. 200-205 [doi]
• Exploiting Hybrid Analysis in Solving Electrical NetworksV. Siva Sankar, H. Narayanan, Sachin B. Patkar. 206-211 [doi]
• The Effect of Filling the Unspecified Values of a Test Set on the Test Set QualityIrith Pomeranz, Sudhakar M. Reddy. 215-220 [doi]
• New Techniques for Accelerating Small Delay ATPG and Generating Compact Test SetsBoxue Yin, Dong Xiang, Zhen Chen. 221-226 [doi]
• TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysisAlejandro Czutro, Ilia Polian, Matthew D. T. Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker. 227-232 [doi]
• An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate DelaysKunal P. Ganeshpure, Sandip Kundu. 233-238 [doi]
• Concept of Crossover Point and its Application on Threshold Voltage Definition for Undoped-Body TransistorsRatul Kumar Baruah, Santanu Mahapatra. 241-246 [doi]
• Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital DesignNishant Chandra, Apoorva Kumar Yati, A. B. Bhattacharyya. 247-252 [doi]
• Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate StackAbhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak. 253-258 [doi]
• Design, Implementation and Validation of an Open Source IP-PBX/VoIP Gateway SoCSpyros Apostolacos, George Lykakis, Apostolos Meliones, Vassilis Vlagoulis, Emmanuel Touloupis, George E. Konstantoulakis. 261-266 [doi]
• Efficient Implementation of Floating-Point Reciprocator on FPGAManish Kumar Jaiswal, Nitin Chandrachoodan. 267-271 [doi]
• ReConfigurable TechnologiesMona Mathur. 272 [doi]
• High-Speed On-Chip Event Counters for Embedded SystemsNilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer. 275-280 [doi]
• A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined RadiosTorsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr. 281-286 [doi]
• Improved-Quality Real-Time Stereo Vision ProcessorSang-Kyo Han, SeongHoon Woo, Mun-Ho Jeong, Bum-Jae You. 287-292 [doi]
• A 7T/14T Dependable SRAM and its Array Structure to Avoid Half SelectionHidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 295-300 [doi]
• A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOSSuresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy. 301-306 [doi]
• Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded SystemsJawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan. 307-312 [doi]
• Encoding of Floorplans through Deterministic PerturbationDebasri Saha, Susmita Sur-Kolay. 315-320 [doi]
• Design Optimization and Automation for Secure Cryptographic CircuitsKuan Jen Lin, Yi Tang Chiu, Shan Chien Fang. 321-326 [doi]
• A Novel Sustained Vector Technique for the Detection of Hardware TrojansMainak Banga, Michael S. Hsiao. 327-332 [doi]
• Efficient Placement of Compressed Code for Parallel DecompressionXiaoke Qin, Prabhat Mishra. 335-340 [doi]
• FPGA Based High Performance Double-Precision Matrix MultiplicationVinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan. 341-346 [doi]
• FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition SystemJ. Manikandan, B. Venkataramani, V. Avanthi. 347-352 [doi]
• A Stitch in Time: Accurate Timekeeping with On-Chip CompensationPrashant Bhargava, Mohit Arora. 353-358 [doi]
• Systematic Methodology for High-Level Performance Modeling of Analog SystemsSoumya Pandit, Chittaranjan A. Mandal, Amit Patra. 361-366 [doi]
• A Comparison of Approaches to Carrier Generation for Zigbee TransceiversLeburu Manojkumar, Arun Mohan, Nagendra Krishnapura. 367-372 [doi]
• A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) LinkVijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar. 373-378 [doi]
• Design and Implementation of Fine-Grain Power Gating with Ground Bounce SuppressionKimiyoshi Usami, Toshiaki Shirai, Tasunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura. 381-386 [doi]
• A Method for the Multi-Net Multi-Pin Routing Problem with Layer AssignmentTuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta. 387-392 [doi]
• A New Hardware Routing Accelerator for Multi-Terminal NetsKaleem Fatima, Rameshwar Rao. 393-398 [doi]
• Simultaneous Routing and Feedthrough Algorithm to Decongest Top ChannelShashank Prasad, Anuj Kumar. 399-403 [doi]
• Metric Based Multi-Timescale Control for Reducing Power in Embedded SystemsNitin Kataria, Forrest Brewer, João Pedro Hespanha, Timothy Sherwood. 407-412 [doi]
• Code Transformations for TLB Power ReductionReiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava. 413-418 [doi]
• Simultaneous Peak Temperature and Average Power Minimization during Behavioral SynthesisVyas Krishnan, Srinivas Katkoori. 419-424 [doi]
• Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm OptimizationRajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil. 427-432 [doi]
• Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design SpaceShubhankar Basu, Balaji Kommineni, Ranga Vemuri. 433-438 [doi]
• A Low Power Architecture to Extend the Tuning Range of a Quadrature ClockRamen Dutta, T. K. Bhattacharyya. 439-444 [doi]
• Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit DesignAngan Das, Ranga Vemuri. 445-450 [doi]
• RADJAM: A Novel Approach for Reduction of Soft Errors in Logic CircuitsKoustav Bhattacharya, Nagarajan Ranganathan. 453-458 [doi]
• Soft Error Rates with Inertial and Logical MaskingFan Wang, Vishwani D. Agrawal. 459-464 [doi]
• Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case StudyUnmesh D. Bordoloi, Samarjit Chakraborty. 465-470 [doi]
• Built in Self Test Based Design of Wave-Pipelined Circuits in ASICsV. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani. 473-478 [doi]
• WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance RequirementsChunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar. 479-484 [doi]
• An Error Model to Study the Behavior of Transient Errors in Sequential CircuitsKarthikeyan Lingasubramanian, Sanjukta Bhanja. 485-490 [doi]
• Analysis of the Energy Quantization Effects on Single Electron Inverter Performance through Noise Margin ModelingSurya Shankar Dan, Santanu Mahapatra. 493-498 [doi]
• Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor ApplicationsSudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi. 499-504 [doi]
• Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube InterconnectsK. C. Narasimhamurthy, Roy P. Paily. 505-510 [doi]
• Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA CircuitsHimanshu Thapliyal, Nagarajan Ranganathan. 511-516 [doi]
• An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing AnalysisRamamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind. 519-524 [doi]
• Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and SolutionsR. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao. 525-530 [doi]
• Unified Challenges in Nano-CMOS High-Level SynthesisSaraju P. Mohanty. 531 [doi]
• Exploring the Limits of Port Reduction in Centralized Register FilesSandeep Sirsi, Aneesh Aggarwal. 535-540 [doi]
• Temperature Aware Scheduling for Embedded ProcessorsRamkumar Jayaseelan, Tulika Mitra. 541-546 [doi]
• SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded SystemsWeixun Wang, Prabhat Mishra, Ann Gordon-Ross. 547-552 [doi]
• H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded ProcessorsSourav Roy. 553-558 [doi]
• Infrastructures for Education, Research and Industry in Microelectronics A Look Worldwide and a Look at IndiaBernard Courtois, Kholdoun Torki, S. Dumont, S. Eyraud, J.-F. Paillotin, G. di Pendina. 561-566 [doi]
• Specification Driven Design of Phase Locked LoopsPrakash Easwaran, Prasenjit Bhowmik, Rupak Ghayal. 569-578 [doi]
• Coping with Variations through System-Level DesignNilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy. 581-586 [doi]