Table of Contents

• Output-Dependent Diagnostic Test GenerationIrith Pomeranz, Sudhakar M. Reddy. 3-8 [doi]
• A Unified Solution to Scan Test Volume, Time, and Power MinimizationZhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya. 9-14 [doi]
• Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory SystemsGautam Hazari, Madhav P. Desai, G. Srinivas. 15-20 [doi]
• A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFETSudipta Sarkar, Ananda S. Roy, Santanu Mahapatra. 21-26 [doi]
• Implementation of a Novel Phoneme Recognition System Using TMS320C6713 DSPJ. Manikandan, B. Venkataramani, M. Bhaskar, K. Ashish, R. Raghul, V. Mathangi. 27-32 [doi]
• Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based CodesUsha S. Mehla, Kankar S. Dasgupta, Niranjan M. Devashrayee. 33-38 [doi]
• Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault EnumerationIrith Pomeranz, Sudhakar M. Reddy. 39-44 [doi]
• A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAMGarima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan. 45-50 [doi]
• Novel Vth Hopping Techniques for Aggressive Runtime Leakage ControlHao Xu, Wen-Ben Jone, Ranga Vemuri. 51-56 [doi]
• Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCsMohammad Arjomand, Hamid Sarbazi-Azad. 57-62 [doi]
• A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement MethodsMing Xu, Gary Gréwal. 63-68 [doi]
• Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic BiochipsYang Zhao, Ryan Sturmer, Krishnendu Chakrabarty, Vamsee K. Pamula. 69-74 [doi]
• Post Assembly Timing Closure for Multi Million Gate ChipsShashank Prasad, Dongzi Liu, Oleg Levitsky, Dave Noice, Shailendra Srivastava. 75-80 [doi]
• Synthesizability of 3 Party Formal Specifications-Does My Controller See Enough?Ansuman Banerjee. 81-86 [doi]
• Channel Optimization for the Design of High Speed I/O linksRohan Mandrekar, Yaping Zhou, Sungjun Chun, Anand Haridass, Jinwoo Choi, Nanju Na, Daniel M. Dreps, Roger D. Weekly, Paul Harvey. 87-92 [doi]
• An Efficient Design of a Reversible Barrel ShifterIrina Hashmi, Hafiz Md. Hasan Babu. 93-98 [doi]
• A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCOSaraju P. Mohanty, Dhruva Ghai, Elias Kougianos. 99-104 [doi]
• A Unified Approach for IP Protection across Design Phases in a Packaged ChipDebasri Saha, Susmita Sur-Kolay. 105-110 [doi]
• Identifying the Bottlenecks to the RF Performance of FinFETsVaidyanathan Subramanian, Abdelkarim Mercha, Bertrand Parvais, Morin Dehan, Guido Groeseneken, Willy M. C. Sansen, Stefaan Decoutere. 111-116 [doi]
• A Novel Circuit to Optimize Access Time and Decoding Schemes in MemoriesSanjeev K. Jain, Krishna Srivastva, Sanjiv Kainth. 117-121 [doi]
• Functional Refinement: A Generic Methodology for Managing ESL AbstractionsSyed Saif Abrar, Aravinda Thimmapuram. 122-127 [doi]
• Safe-ERfairArnab Sarkar, Rahul Nanda, Sujoy Ghose, P. P. Chakrabarti. 128-133 [doi]
• Exploring Use of NoC for Reconfigurable Video CodingAlpesh Patel, Hemangee K. Kapoor. 134-139 [doi]
• Coverage Management with Inline Assertions and Formal Test PointsAritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti. 140-145 [doi]
• Instruction Selection in ASIP Synthesis Using Functional MatchingNidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar. 146-151 [doi]
• Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter ProductRamen Dutta, Tarun Kanti Bhattacharyya, Xiang Gao, Eric A. M. Klumperink. 152-157 [doi]
• Inexact Decision Circuits: An Application to Hamming Weight Threshold VotingBharghava Rajaram, Abinesh Ramachandran, Suresh Purini, Govindarajulu Regeti. 158-163 [doi]
• Transition Inversion Based Low Power Data Coding Scheme for Buffered Data TransferAbinesh Ramachandran, Bharghava Rajaram, Suresh Purini, Govindarajulu Regeti. 164-169 [doi]
• Modeling of RF- MEMS BAW ResonatorAmbarish Roy, Bradley P. Barber, Kanti Prasad. 170-175 [doi]
• Accelerating Synchronous Sequential Circuits Using an Adaptive ClockArijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta. 176-181 [doi]
• 23.97GHz CMOS Distributed Voltage Controlled Oscillators with Inverter Gain Cells and Frequency Tuning by Body Bias and MOS Varactors ConcurrentlyKalyan Bhattacharyya. 182-187 [doi]
• Design Considerations for BEOL MIM Capacitor Modeling in RF CMOS ProcessesShyam Parthasarathy, Balaji Swaminathan, Ananth Sundaram, Robert A. Groves. 188-193 [doi]
• RF SOI Switch FET Design and Modeling Tradeoffs for GSM ApplicationsShyam Parthasarathy, Amit Trivedi, Saurabh Sirohi, Robert A. Groves, Michael Olsen, Yogesh S. Chauhan, Michael Carroll, Dan Kerr, Ali Tombak, Phil Mason. 194-199 [doi]
• Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed PerformanceGlenn Leary, Karam S. Chatha. 200-205 [doi]
• Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced PowerZichu Qi, Qi Guo, Ge Zhang, Xiangku Li, Weiwu Hu. 206-211 [doi]
• Modeling of High Frequency Noise in SOI MOSFETsMuthubalan Varadharajaperumal, Saurabh Sirohi, Sourabh Khandelwal, Ethirajan Tamilmani, Vaidyananthan Subramanian. 212-217 [doi]
• Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory ArrayVinayak Honkote, Baris Taskin. 218-223 [doi]
• On Electrical Modeling of Imperfect Diffusion PatterningTuck Boon Chan, Puneet Gupta. 224-229 [doi]
• A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier ApplicationsRadhakrishnan Sithanandam, Mamidala Jagadesh Kumar. 230-234 [doi]
• Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage OutputsHimanshu Thapliyal, Nagarajan Ranganathan. 235-240 [doi]
• An L-band Fractional-N Synthesizer with Noise-Less Active Capacitor ScalingDebapriya Sahu, Saravana Ganeshan, Ashish Lachhwani, Rittu Sachdev, B. G. Chandrashekar. 241-245 [doi]
• A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nmShailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik. 252-257 [doi]
• A Reconfigurable Architecture for Secure Multimedia DeliveryAmit Pande, Joseph Zambreno. 258-263 [doi]
• A Hardware Scheduler for Real Time Multiprocessor System on ChipNikhil Gupta, Suman Kalyan Mandal, Javier Malave, Ayan Mandal, Rabi N. Mahapatra. 264-269 [doi]
• Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O LinkLeneesh Raghavan, Ting Wu. 270-275 [doi]
• Impact of Temperature on Test QualityLavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti. 276-281 [doi]
• A Methodology for Power Aware High-Level Synthesis of Co-processors from Software AlgorithmsSumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla. 282-287 [doi]
• Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial CoefficientsSuraj Sindia, Virendra Singh, Vishwani D. Agrawal. 288-293 [doi]
• An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron TechnologySamiran DasGupta, Pradip Mandal. 294-299 [doi]
• High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction TechniqueKunal Desai, Rajasekhar Nagulapalli, Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, Vijay Khawshe. 300-305 [doi]
• Pinpointing Cache Timing Attacks on AESChester Rebeiro, Mainack Mondal, Debdeep Mukhopadhyay. 306-311 [doi]
• A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS ProcessArunkumar Salimath, Chandrajit Debnath, Kallol Chatterjee, Sushanta K. Mandal. 312-317 [doi]
• A Hierarchical Methodology for Word-Length Optimization of Signal Processing SystemsKarthick Parashar, Romuald Rocher, Daniel Menard, Olivier Sentieys. 318-323 [doi]
• On-Chip Inductor-Less DC-DC Boost Converter with Non-overlapped Rotational-Interleaving SchemeTamal Das, Pradip Mandal. 324-329 [doi]
• 4 GHz 130nm Low Voltage PLL Based on Self Biased TechniqueBiju Viswanathan, Vijay Viswam, R. Kulanthaivelu, Joseph J. Vettickatt, S. R. Ramya Nair, Lekshmi S. Chandran. 330-334 [doi]
• An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock LoopsBalaji Srinivasan, Vinay Bhaskar Chandratre. 335-338 [doi]
• Clocking-Based Coplanar Wire Crossing Scheme for QCARajeswari Devadoss, Kolin Paul, M. Balakrishnan. 339-344 [doi]
• Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay FaultsShehzad Hasan, Ajoy Kumar Palit, Walter Anheier. 345-350 [doi]
• Synchronized Generation of Directed Tests Using Satisfiability SolvingXiaoke Qin, Mingsong Chen, Prabhat Mishra. 351-356 [doi]
• Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time SystemsWeixun Wang, Prabhat Mishra. 357-362 [doi]
• An Efficient Method for Bottom-Up Extraction of Analog Behavioral Model ParametersSrikanth Pam, Anirban Krishna Bhattacharya, Siddhartha Mukhopadhyay. 363-368 [doi]
• Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability DegradationAmlan Ghosh, Rob Franklin, Richard B. Brown. 369-374 [doi]
• Rethinking Threshold Voltage Assignment in 3D Multicore DesignsKoushik Chakraborty, Sanghamitra Roy. 375-380 [doi]
• Towards Active-Passive Co-synthesis of Multi-gigaHertz Radio Frequency CircuitsRitochit Chakraborty, Arun V. Sathanur, Vikram Jandhyala. 381-386 [doi]
• Optical Lithography Simulation with Focus Variation using Wavelet TransformRance Rodrigues, Sandip Kundu. 387-392 [doi]
• On Minimization of Test Application Time for RASRaghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh. 393-398 [doi]
• Analyzing Energy-Delay Behavior in Room Temperature Single Electron TransistorsVinay Saripalli, Vijaykrishnan Narayanan, Suman Datta. 399-404 [doi]
• RTL Hardware IP Protection Using Key-Based Control and Data Flow ObfuscationRajat Subhra Chakraborty, Swarup Bhunia. 405-410 [doi]
• An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI InterconnectsSandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas. 411-416 [doi]
• Front-End Design Flows for Systems on Chip: An Embedded TutorialAnshul Kumar, Preeti Ranjan Panda. 417-422 [doi]
• Electrical Modeling of Lithographic ImperfectionsTuck Boon Chan, Rani S. Ghaida, Puneet Gupta. 423-428 [doi]
• The Dawn of 22nm Era: Design and CAD ChallengesRuchir Puri, David S. Kung. 429-433 [doi]
• Robust System DesignSubhasish Mitra. 434-439 [doi]
• FinFET SRAM DesignRajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj. 440-445 [doi]
• Processor Architecture Design Using 3D Integration TechnologyYuan Xie. 446-451 [doi]
• Digital Microfluidic Biochips: A Vision for Functional Diversity and More than MooreKrishnendu Chakrabarty. 452-457 [doi]
• Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous ComponentsKaushik Roy, Byunghoo Jung, Anand Raghunathan. 464-469 [doi]