Abstract is missing.
- Test methodology for embedded cores which protects intellectual propertyK. De. 2-9 [doi]
- Testing Embedded Cores Using Partial Isolation RingsNur A. Touba, Bahram Pouya. 10-16 [doi]
- A practical approach to instruction-based test generation for functional modules of VLSI processorsKazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada. 17-23 [doi]
- Assessing SRAM test coverage for sub-micron CMOS technologiesV. Kim, T. Chen. 24-30 [doi]
- Experimental fault analysis of 1 Mb SRAM chipsH. Goto, S. Nakamura, K. Iwasaki. 31-36 [doi]
- Disturb Neighborhood Pattern Sensitive FaultA. J. van de Goor, Issam B. S. Tlili. 37-47 [doi]
- Methods to reduce test application time for accumulator-based self-testAlbrecht P. Stroele, Frank Mayer. 48-53 [doi]
- Implicit test pattern generation constrained to cellular automata embeddingFranco Fummi, Donatella Sciuto. 54-59 [doi]
- Cellular automata for deterministic sequential test pattern generationSilvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 60-67 [doi]
- Bridges in sequential CMOS circuits: current-voltage signaturRosa Rodríguez-Montañés, Joan Figueras. 68-73 [doi]
- Using fault sampling to compute I/sub DDQ/ diagnostic test setYiming Gong, Sreejit Chakravarty. 74-79 [doi]
- A novel probabilistic approach for IC diagnosis based on differential quiescent current signaturesClaude Thibeault. 80-87 [doi]
- High Quality Robust Tests for Path Delay FaultsLiang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer. 88-93 [doi]
- An optimized BIST test pattern generator for delay testingPatrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch. 94-100 [doi]
- On the Fault Coverage of Interconnect DiagnosisXiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi. 101-109 [doi]
- Analysis of Ground Bounce in Deep Sub-Micron CircuitsYi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer. 110-116 [doi]
- Switch-level modeling of feedback faults using global oscillation controlPeter Dahlgren. 117-122 [doi]
- Built-in parametric test for controlled impedance I/OsT. Haulin. 123-129 [doi]
- Using ATPG for clock rules checking in complex scan designPeter Wohl, John A. Waicukauski. 130-136 [doi]
- A Novel Solution for Chip-Level Functional Timing VerificationRathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham. 137-142 [doi]
- Incremental logic rectificationShi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng. 143-149 [doi]
- Polynomial Formal Verification of MultipliersMartin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor. 150-157 [doi]
- CLP-based Multifrequency Test Generation for Analog CircuitsAbdessatar Abderrahman, Eduard Cerny, Bozena Kaminska. 158-165 [doi]
- Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test MethodologyKarim Arabi, Bozena Kaminska. 166-171 [doi]
- Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test GenerationZbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz. 172-176 [doi]
- Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMSNihal J. Godambe, C.-J. Richard Shi. 177-183 [doi]
- Systems On Silicon: Design and Test ChallengesJ. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian. 184-185 [doi]
- Will 0.1um Digital Circuits Require Mixed-Signal TestingMelvin A. Breuer, Bozena Kaminska, J. McDermid, V. Rayapathi, Donald L. Wheater. 186-187 [doi]
- Fast Algorithms for Static Compaction of Sequential Circuit Test VectorsMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. 188-195 [doi]
- Diagnostic Test Pattern Generation for Sequential CircuitsIsmed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs. 196-202 [doi]
- Critical hazard free test generation for asynchronous circuitsAjay Khoche, Erik Brunvand. 203-209 [doi]
- Highly testable and compact single output comparatorCecilia Metra, Michele Favalli, Bruno Riccò. 210-215 [doi]
- Self-exercising self testing k-order comparatorsXrysovalantis Kavousianos, Dimitris Nikolos. 216-221 [doi]
- Exact probabilistic analysis of error detection for parity checkersValery A. Vardanian. 222-229 [doi]
- Test of RAM-based FPGA: methodology and application to the interconnectMichel Renovell, Joan Figueras, Yervant Zorian. 230-237 [doi]
- Robust Sequential Fault Testing of Iterative Logic ArraysDimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis. 238-244 [doi]
- A new approach for testing artificial neural networksC. A. Fleischer, Lee A. Belfore II. 245-251 [doi]
- Test Synthesis for DC Test and Maximal Diagnosis of Switched-Capacitor CircuitsChristian Dufaza, Hassan Ihs. 252-260 [doi]
- Low-cost and efficient digital-compatible BIST for analog circuits using pulse response samplingPramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi. 261-266 [doi]
- Functional test pattern generation for CMOS operational amplifierSoon-Jyh Chang, Chung-Len Lee, Jwu E. Chen. 267-273 [doi]
- SPITFIRE: scalable parallel algorithms for test set partitioned fault simulationDilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee. 274-281 [doi]
- The Dynamic Rollback Problem in Concurrent Event-Driven Fault SimulationLaura Farinetti, Pier Luca Montessoro. 282-287 [doi]
- Static logic implication with application to redundancy identificationJian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel. 288-295 [doi]
- Automated test pattern generation for analog integrated circuitsWim Verhaegen, Geert Van der Plas, Georges G. E. Gielen. 296-301 [doi]
- A DFT Technique for Analog-to-Digital Converters with digital correctionEduardo J. Peralías, Adoración Rueda, José L. Huertas. 302-307 [doi]
- Determination of coherence errors in ADC spectral domain testingW. D. Bartlett. 308 [doi]
- ATE for VLSI: What Challenges Lie Ahead?D. Cheung, Bernd Koenemann, S. Nishtala, B. West, D. Wu. 318-319 [doi]
- Hardware Test: Can We Learn from Software Testing?J. Abraham, P. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse. 320-321 [doi]
- Testability of Sequential Circuits with Multi-Cycle False PathPriyank Kalla, Maciej J. Ciesielski. 322-328 [doi]
- EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverageIrith Pomeranz, Sudhakar M. Reddy. 329-335 [doi]
- On n-detection test sequences for synchronous sequential circuits343Irith Pomeranz, Sudhakar M. Reddy. 336-343 [doi]
- An on-line testable UART implemented using IFISJ. Yeandel, D. Thulborn, S. Jones. 344-349 [doi]
- A linear code-preserving signature analyzer COPMISRAndrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan. 350-355 [doi]
- A high-level synthesis approach to design of fault-tolerant systemsGiacomo Buonanno, M. Pugassi, Mariagiovanna Sami. 356-363 [doi]
- ATPG for scan chain latches and flip-flopsSamy Makar, Edward J. McCluskey. 364-369 [doi]
- High-Level Synthesis for Orthogonal ScaRobert B. Norwood, Edward J. McCluskey. 370-375 [doi]
- BIST TPGs for Faults in Board Level Interconnect via Boundary ScanChen-Huan Chiang, Sandeep K. Gupta. 376-383 [doi]
- A methodolgy for characterizing cell testabilityA. Jee, F. Joel Ferguson. 384-390 [doi]
- Fault coverage of a long random test sequence estimated from a short simulationV. Prepin, R. David. 391-398 [doi]
- Random pattern testability of memory control logicJacob Savir. 399-409 [doi]
- Obtaining High Fault Coverage with Circular BIST Via State SkippingNur A. Touba. 410-415 [doi]
- Salvaging test windows in BIST diagnosticJacob Savir. 416-425 [doi]
- On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic AlgorithmsCan Ökmen, Martin Keim, Rolf Krieger, Bernd Becker. 426-433 [doi]
- Differential Sensing Strategy for Dynamic Thermal Testing of ICsJosep Altet, Antonio Rubio. 434-439 [doi]
- Integrating on-chip temperature sensors into DfT schemes and BIST architecturesVladimir Székely, Márta Rencz, Bernard Courtois. 440-445 [doi]
- SHOrt voltage elevation (SHOVE) test for weak CMOS ICsJonathan T.-Y. Chang, Edward J. McCluskey. 446 [doi]
- Power Dissipation During Testing: Should We Worry About it?Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian. 456-457 [doi]
- Microprocessor Test and Validation: Any New Avenues?Magdy S. Abadir, Jacob A. Abraham, H. Hao, C. Hunter, Wayne M. Needham, Ron G. Walther. 458-464 [doi]
- An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testingPhil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken. 459 [doi]