Table of Contents

• VTS 1999 Keynote Address Embedded Test OR External TestVinod K. Agarwal. 2-7 [doi]
• Design Technology Research and Education for Deep-Submicron Systems of the Next CenturyHugo De Man. 8-15 [doi]
• Testing High Speed VLSI Devices Using Slower TestersAngela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar. 16-21 [doi]
• Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring CountersKrishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar. 22-27 [doi]
• The Limits of Digital Testing for Dynamic CircuitsR. Dean Adams, Edmond S. Cooley. 28-33 [doi]
• Instruction Randomization Self Test For Processor CoresKen Batcher, Christos A. Papachristou. 34-40 [doi]
• Testing of Non-Isolated Embedded Legacy Cores and their Surrounding LogicIrith Pomeranz, Yervant Zorian. 41-48 [doi]
• A New Totally Error Propagating Compactor for Arbitrary Cores with Digital InterfacesMichael Gössel, A. A. Morosov, Egor S. Sogomonyan. 49-57 [doi]
• Multiple Design Error Diagnosis and Correction in Digital VLSI CircuitsAndreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs. 58-63 [doi]
• A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault SimulationsHiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu. 64-69 [doi]
• Simulation-Based Design Error Diagnosis and Correction in Combinational Digital CircuitsDebashis Nayak, D. M. H. Walker. 70-79 [doi]
• Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and TestMichael A. Margolese, F. Joel Ferguson. 80-85 [doi]
• Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer TechnologiesMichael Nicolaidis. 86-94 [doi]
• Test Generation for Ground Bounce in Internal Logic CircuitryYi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer. 95-105 [doi]
• Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICsJosef Schmid, Joachim Knäblein. 106-113 [doi]
• Scan Vector Compression/Decompression Using Statistical CodingAbhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba. 114-120 [doi]
• Partial Scan Using Multi-Hop State Reachability AnalysisSameer Sharma, Michael S. Hsiao. 121-127 [doi]
• Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ CoverageRobert C. Aitken. 128-134 [doi]
• Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOSTh. Calin, Lorena Anghel, Michael Nicolaidis. 135-142 [doi]
• On the Comparison of IDDQ and IDDQ TestingClaude Thibeault. 143-151 [doi]
• A Flexible Path Selection Procedure for Path Delay Fault TestingIrith Pomeranz, Sudhakar M. Reddy. 152-159 [doi]
• Delay Fault Testing of Designs with Embedded IP CoresHyungwon Kim, John P. Hayes. 160-167 [doi]
• Adaptive Techniques for Improving Delay Fault DiagnosisJayabrata Ghosh-Dastidar, Nur A. Touba. 168-172 [doi]
• On n-Detection Test Sets and Variable n-Detection Test Sets for Transition FaultsIrith Pomeranz, Sudhakar M. Reddy. 173-181 [doi]
• Validation Vector Grade (VVG): A New Coverage Metric for Validation and TestPradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul. 182-188 [doi]
• Verification of Processor MicroarchitecturesJian Shen, Jacob A. Abraham. 189-194 [doi]
• Techniques to Encode and Compress Fault DictionariesSreejit Chakravarty, Vinodh Gopal. 195-200 [doi]
• Implication and Evaluation Techniques for Proving Fault EquivalenceEnamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana. 201-213 [doi]
• Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical SimulationPramodchandran N. Variyam, Junwei Hou, Abhijit Chatterjee. 214-219 [doi]
• Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal CircuitsJiun-Lang Huang, Chen-Yang Pan, Kwang-Ting Cheng. 220-225 [doi]
• Test Metrics for Analog Parametric FaultsStephen K. Sunter, Naveena Nagi. 226-235 [doi]
• Comparative Study of CA-based PRPGs and LFSRs with Phase ShiftersJanusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer. 236-245 [doi]
• An Efficient BIST Method for Small BuffersWen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee. 246-251 [doi]
• An Effective BIST Architecture for Sequential Fault Testing in Array MultipliersMihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian. 252-259 [doi]
• A Fault Simulation Based Test Pattern Generator for Synchronous Sequential CircuitsRuifeng Guo, Irith Pomeranz, Sudhakar M. Reddy. 260-267 [doi]
• REDO - Probabilistic Excitation and Deterministic Observation - First Commercial ExperimenMichael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer. 268-274 [doi]
• Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential CircuitsSudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin. 275-283 [doi]
• A Novel Test Methodology for MEMS Magnetic MicromotorsBruce C. Kim, Krishna Marella. 284-289 [doi]
• A New Bare Die Test MethodologyZao Yang, K.-T. Cheng, K. L. Tai. 290-295 [doi]
• Hierarchical Test Generation for Analog Circuits Using Incremental Test DevelopmentRamakrishna Voorakaranam, Abhijit Chatterjee. 296-303 [doi]
• A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal CircuitsIyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis. 304-310 [doi]
• A Current Integrator for BIST of Mixed-Signal ICsSassan Tabatabaei, André Ivanov. 311-318 [doi]
• A Test Point Insertion Algorithm for Mixed-Signal CircuitsJinyan Zhang, Sam D. Huynh, Mani Soma. 319-325 [doi]
• Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling TechniqueMarcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. 326-332 [doi]
• Behavioral Fault Modeling in a VHDL Synthesis EnvironmentRonald J. Hayne, Barry W. Johnson. 333-340 [doi]
• RT-level TPG Exploiting High-Level Synthesis InformationSilvia Chiusano, Fulvio Corno, Paolo Prinetto. 341-353 [doi]
• Modular TSC Checkers for Bose-Lin and Bose CodesXrysovalantis Kavousianos, Dimitris Nikolos. 354-360 [doi]
• Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting CodeAlbrecht P. Stroele, Steffen Tarnick. 361-369 [doi]
• Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel CircuitsDebaleena Das, Nur A. Touba. 370-377 [doi]
• Maximal Diagnosis of Interconnects of Random Access MemoriesJun Zhao, Fred J. Meyer, Fabrizio Lombardi. 378-383 [doi]
• Error Detecting Refreshment for Embedded DRAMsSybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik. 384-390 [doi]
• A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test UnitsKamran Zarrineh, Shambhu J. Upadhyaya. 391-397 [doi]
• TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BISTSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. 398-406 [doi]
• A Test Vector Inhibiting Technique for Low Energy BIST DesignPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. 407-412 [doi]
• Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan AccessCarter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud. 413-419 [doi]
• Analyzing the Need for ATPG Targeting GOS DefectsEugeni Isern, Miquel Roca, Jaume Segura. 420-425 [doi]
• On the Evaluation of Arbitrary Defect Coverage of Test SetsAnkur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita. 426-432 [doi]
• Defect-Oriented Test SchedulingWanli Jiang, Bapiraju Vinnakota. 433-439 [doi]
• PADded Cache: A New Fault-Tolerance Technique for Cache MemoriesPhilip P. Shirvani, Edward J. McCluskey. 440-445 [doi]
• Low-Cost On-Line Test for Digital FiltersIsmet Bayraktaroglu, Alex Orailoglu. 446-451 [doi]
• Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM Maurizio Rebaudengo, Matteo Sonza Reorda. 452-459 [doi]
• A Systematic DFT Procedure for Library CellsJingjing Xu, Rahul Kundu, F. Joel Ferguson. 460-466 [doi]
• Instruction-Driven Wake-Up Mechanisms for Snoopy TAP ControllerDebashis Bhattacharya. 467-472 [doi]
• From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1Gustavo R. Alves, Jose M. Martins Ferreira. 473-486 [doi]